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24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 1 cover page amd-8131 tm hypertransport tm pci-x ? tunnel data sheet 1overview the amd-8131 tm hypertransport tm pci-x ? tunnel (referred to as the ic in this document) is a hypertransport? technology (referred to as link in this document) tunnel developed by amd that provides two pci-x bridges. 1.1 device features ? hypertransport technology tunnel with side a and side b. ? side a is 16 bits (input and output); side b is 8 bits. ? either side may connect to the host or to a downstream hypertransport technology compliant device. ? each side supports hypertransport technol- ogy-defined reduced bit widths: 8-bit, 4-bit, and 2-bit. ? each side supports transfer rates of 1600, 1200, 800, and 400 mega-transfers per sec- ond. ? maximum bandwidth is 6.4 gigabytes per second across side a (half upstream and half downstream) and 3.2 gigabytes per second across side b. ? independent transfer rate and bit width selection for each side. ? link disconnect protocol supported. ? two pci-x (rev. 1.0) bridges: bridge a and bridge b. ? each bridge supports a 64-bit data bus. ? each bridge supports operational modes of pci-x and legacy pci revision 2.2 protocol. ? bridges support 133, 100, and 66 mhz transfer rates in pci-x mode. ? bridges support 66 and 33 mhz transfer rates in pci mode. ? independent transfer rates and operational modes for each bridge. ? each bridge includes support for up to 5 pci masters with clock, request, and grant sig- nals. ? each bridge includes an ioapic with four redirection registers. legacy interrupt con- troller and ioapic modes supported. ? shpc-compliant hot plug controller and support. ? 37.5 x 37.5 millimeter, 829-pin bga package. ? 3.3 volt pci-x signaling; 1.2 volt link signaling; 1.8 volt core. figure 1: system block diagram. amd-8131 tm device host hypertransport tm link 16 bits upstream, 16 bits downstream hypertransport link 8 bits upstream, 8 bits downstream downstream device tunnel side a side b pci-x bridge a pci-x bridge b slots slots
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 2 trademarks amd, the amd arrow logo, and combinations thereof, and amd-8131 are trademarks of advanced micro devices, inc. hypertransport is a licensed trademark of the hypertransport technology consortium. pci-x is a registered trademark of the pci-special interest group (pci-sig). other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 2004 advanced micro devices, inc. all rights reserved.the contents of this document are provided in connec- tion with advanced micro devices, inc. ("amd") products. amd makes no representations or warranties with respect to the accuracy or complete- ness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or other- wise, to any intellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in sys- tems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 3 table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 device features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 tunnel link signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 pci-x ? signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 test and miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.1 power plane sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 functional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.1 non-hot plug initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.2 hot plug initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.1 systemboard requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.2 characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.3 clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 tunnel links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4.1 link phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 pci-x ? bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.1 tags, unitids, seqids and ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.2 interrupt controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.2.1 error nmi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.3 hot plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.3.1 multi-slot hot plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.3.2 single-slot hot plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 4.5.3.3 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.3.3.1 serial data from the power controllers to the ic . . . . . . . . . . . . . . . . . . . . . . . 28 4.5.3.3.2 serial data from the ic to the power controllers . . . . . . . . . . . . . . . . . . . . . . . 29 4.5.3.4 shpc interrupts, events, and errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5.3.5 reset to hot plug slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5.4 pci-x ? phy compensation update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5.5 transactions claimed by the bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5.6 various behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5.7 error conditions and handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.6 performance-related information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1 bandwidth percentage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.2 latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 register overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.1 configuration space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.2 register naming and description conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 4 5.2 pci-x ? bridge configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 pci-x ioapic configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4 ioapic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5 shpc working registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.1 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7 ball designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8 package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.1 high impedance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.2 nand tree mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10.1 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 5 list of figures figure 1: system block diagram.................................................................................................. ................. 1 figure 2: systemboard clocking. ................................................................................................. ............... 17 figure 3: correction for characterization. ...................................................................................... ............ 18 figure 4: system diagram for multiple hot plug slots on a bridge. ............................................................ 22 figure 5: system diagram of pme# signals. ....................................................................................... ....... 23 figure 6: system diagram of m66en signals. ...................................................................................... ..... 23 figure 7: multi-slot hot plug enable/disable sequence........................................................................... .... 24 figure 8: single-slot hot plug system diagram................................................................................... ........ 25 figure 9: single-slot hot plug enable/disable sequence.......................................................................... .... 26 figure 10: single-slot hot plug m66en connections. .............................................................................. .... 26 figure 11: hot plug serial interface connections................................................................................ .......... 27 figure 12: configuration space. ................................................................................................. .................. 40 figure 13: ball designations. ................................................................................................... ..................... 77 figure 14: package mechanical drawing. .......................................................................................... ........... 82 figure 15: nand tree. ........................................................................................................... ...................... 83
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 6 list of tables table 1: io signal types. ....................................................................................................... ...................... 7 table 2. signal isolation groups................................................................................................ ................ 22 table 3: channel 00b, interrupt capable serial hot plug data to the ic..................................................... 28 table 4: channel 01b, non-interrupt capable serial hot plug data to the ic. ............................................ 29 table 5: serial hot plug data from the ic to the power controller. ........................................................... 29 table 6: bandwidth percentages. ................................................................................................. ............. 38 table 7: some latencies......................................................................................................... .................... 39 table 8: configuration spaces................................................................................................... ................ 41 table 9: memory mapped address spaces........................................................................................... ...... 41 table 10: register attributes. .................................................................................................. .................... 41 table 11: absolute maximum ratings. ............................................................................................. ........... 74 table 12: operating ranges. ..................................................................................................... ................... 74 table 13: current and power consumption. ........................................................................................ ........ 75 table 14: dc characteristics for signals on the vdd33 power plane. ....................................................... 75 table 15: ac requirements for refclk. ........................................................................................... ....... 76 table 16: ac data for pci clocks. ............................................................................................... ............... 76 table 17: ac data for pci bus. .................................................................................................. ................. 76 table 18: alphabetical listing of signals a_ack64# to b_preset#. ..................................................... 78 table 19: alphabetical listing of signals b_req0# to vdd18. ................................................................ 79 table 20: alphabetical listing of signals vdd18 to vss.......................................................................... .80 table 21: test modes............................................................................................................ ....................... 83
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 7 2 ordering information 3 signal descriptions 3.1 terminology see section 5.1.2 for a description of the register naming convention used in this document. see the amd-8131 tm hypertransport tm pci-x ? tunnel design guide for additional information. signals with a # suffix are active low. signals described in this chapter utilize the following io cell types: the following provides definitions and reference data about each of the ic pins. during reset provides the state of the pin while reset# is asserted. after reset provides the state of the pin immediately after reset# is deasserted. func. means that the pin is functional and operating per its defined function. name notes input input signal only. output output signal only. this includes outputs that are capable of being in the high-impedance state. od open drain output. these signals are driven low and expected to be pulled high by external circuitry. io input or output signal. iod input or open-drain output. analog analog signal. w/pu with pullup. the signal includes a pullup resistor to the signals power plane. the resistor value is nomi- nally 8k ohms. table 1: io signal types. amd-8131 family/core amd-8131 tm device package type bl = organic ball grid array with lid case temperature c = commercial temperature range bl c
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 8 3.2 tunnel link signals the following are signals associated with the hypertransport links. [b, a] in the signal names below refer to the a and b sides of the tunnel. [p, n] are the positive and negative sides of differential pairs. * the signals connected to the a side of the tunnel are powered by vdd12a and the signals connected to the b side of the tunnel are powered by vdd12b. ** diff high and diff low for these link pins specify differential high and low; e.g., diff high specifies that the _p signal is high and the _n signal is low. if one of the sides of the tunnel is not used on a platform, then the unconnected link should be treated as fol- lows, for every 10 differential pairs: connect all of the _p differential inputs together and through a resistor to vss; connect all the _n differential inputs together and through a resistor to vdd12; leave the differential out- puts unconnected. if there are unused link signals on an active link (because the ic is connected to a device with a reduced bit width), then the unused differential inputs and outputs should also be connected in this way. pin name and description io cell type power plane* during reset after reset ldtcomp[3:0]. link compensation pins for both sides of the tunnel. these are designed to be connected through resistors as follows: bit function external connection [0] positive receive compensation resistor to vdd12b [1] negative receive compensation resistor to vss [3, 2] transmit compensation resistor from bit [2] to bit [3] these resistors are used by the compensation circuit. the output of this circuit is combined with deva:0x[e8, e4, e0] to determine compensation values that are passed to the link phys. analog vdd- 12a lracad_[p, n][15:0]; lrbcad_[p, n][7:0]. receive link command-address- data bus. link input vdd12 lraclk[1, 0]_[p, n]; lrbclk0_[p, n]. receive link clock. link input vdd12 lr[b, a]ctl_[p, n]. receive link control signal. link input vdd12 ltacad_[p, n][15:0]; ltbcad_[p, n][7:0]. transmit link command-address- data bus. link output vdd12 diff high** func. ltaclk[1, 0]_[p, n]; ltbclk0_[p, n]. transmit link clock. link output vdd12 func. func. lt[b, a]ctl_[p, n]. transmit link control signal. link output vdd12 diff low** func.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 9 3.3 pci-x ? signals [b, a] in the following signal names is used to differentiate between pci-x bridge a and pci-x bridge b. normal refers to non-hot plug mode (deva:0x48[hpenb, hpena]) or hot plug mode with external isola- tion switches (dev[b, a]:0x40[hpsss#]); single slot hp refers to hot plug mode while dev[b, a]:0x40[hpsss#] is low. when in normal mode, pci-x signals that typically connect to the slot are placed into the during reset state when [b, a]_preset# is asserted; the other signals are placed into the during reset state only when reset# is asserted. the single slot hp, during reset column refers to while reset# is asserted for all the signals. pin name and description io cell type power plane normal single slot hp during reset after reset during reset after reset [b, a]_ack64#. pci-x ? acknowledge for 64-bit transfers. io vdd33 3-state 3-state low low [b, a]_ad[63:0]. pci-x ? address-data bus. io vdd33 low parked low low [b, a]_cbe_l[7:0]. pci-x ? command-byte enable bus. io vdd33 low parked low low a_compat. strapping option to specify if pci-x bridge a is the default bus in the system. this may only be associated with pci-x ? bridge a. see also deva:0x48[compat]. input vdd33 [b, a]_devsel#. pci-x device select signal. during reset, these signals may be 3-state or they may be driven, based on the requirements of the pci-x initialization pattern. io vdd33 see left 3-state low low [b, a]_frame#. pci-x ? frame signal. io vdd33 3-state 3-state low low [b, a]_gnt[4:0]#. pci-x ? master grant signals. some of these signals are an input while pwrok is deasserted; all other times, they are outputs. [b, a]_gnt[4:3]# each require a strapping resistor to help specify the bridge operationg frequency after a pwrok reset; see section 4.2. note: a_gnt[2:1] require weak pull-up resistors to vdd33. b_gnt2# is an input while pwrok is low and an output at all other times. as an input, it is used to specify the default state of devb:0x40[hpsss#]. hpsss# specifies if the ic supports a single hot plug slot on the bridge without external isolation switches. a weak resistor should be tied from this signal to vdd33 or to ground. [b, a]_hpsorlc. hot plug serial output reset latch clock output (alternate functions to [b, a]_gnt4# selected by hot plug mode, deva:0x48[hpena, hpenb]). these are used in support of the hot plug serial interface. see section 4.5.3.3 for details. io (see left) vdd33 high high [0] is low; [4:1] are high [0] is low; [4:1] are high [b, a]_irdy#. pci-x ? master ready signal. io vdd33 3-state 3-state low low
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 10 [b, a]_m66en. frequency select input for [b, a]_pclk while in conventional pci mode. when not in hot plug mode, the state of this signal is captured at the rising edge [b, a]_preset# and (see section 4.2.1). after the corresponding [b, a]_preset# signal goes high, the state of [b, a]_m66en is ignored. in hot plug mode, this signal may be driven low as an output after initialization. iod vdd33 3-state 3-state low low [b, a]_par. pci-x ? parity signal. io vdd33 low func. low low [b, a]_par64. pci-x ? upper 32-bit parity signal for 64-bit transfers. io vdd33 low func. low low [b, a]_pcixcap. pci-x ? frequency capabilities selection. the state of this signal is captured at the rising edge [b, a]_preset# and used to determine the bus mode (see section 4.2.1). after the corresponding [b, a]_preset# signal goes high, the state of [b, a]_pcixcap is ignored. input vdd33 [b, a]_pclk[4:0]. up to 133 mhz pci-x ? clock outputs. [b, a]_hpsid. hot plug serial input data (alternative function to [b, a]_pclk4# selected by hot plug mode, deva:0x48[hpena, hpenb]). see section 4.5.3.3 for details. io (see left) vdd33 func. func. [4:1]: func. [0]: low [4:1]: func. [0]: low [b, a]_perr#. pci-x ? parity error. this signal is only applicable to parity errors on the secondary pci-x ? bus interface. io vdd33 3-state 3-state low low [b, a]_pirq[a, b, c, d]#. pci-x ? interrupt requests. [b, a]_pirqa# may be an input or an open-drain output in support of the hot plug controller. [b, a]_pirq[b, c, d]# are inputs only. iod; input vdd33 3-state 3-state low low [b, a]_pllclko. pll clock output. see section 4.3 for details. output vdd33 func. func. func. func. [b, a]_pllclki. pll clock input. see section 4.3 for details. input vdd33 [b, a]_pme#. power management event interrupt. the ic asserts this signal when shpc-defined power management events occur. this signal is typically connected to the system southbridge, where it may be used to initate system state transitions. od vdd33 3-state 3-state 3-state 3-state [b, a]_preset#. secondary pci bus reset. this is asserted whenever reset# is asserted or when programmed by dev[b, a]:0x3c[sbrst]. assertion of this pin does not reset any logic internal to the ic. note: the pci requirement for a delay between the rising edge of rst# and the first configuration access is not enforced by the ic with hardware; it is expected that this requirement be enforced through software. in hot plug mode, this is connected to [b, a]_hpsorr# of the power controller. see section 4.5.3.3 for details. output vdd33 low high low high pin name and description io cell type power plane normal single slot hp during reset after reset during reset after reset
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 11 [b, a]_req[4:0]#. pci-x ? master request input signals. a_req[2:0]# are used for test-mode selection; see section 9. [b, a]_hpsolc. hot plug serial output latch clock (alternative function to [b, a]_req4 selected by hot plug mode, deva:0x48[hpena, hpenb]). see section 4.5.3.3 for details. io (see left) vdd33 reqs are inputs; hp- solc: high reqs are inputs; hp- solc: high [0]: low; [3:1]: inputs; hp- solc: high [0]: low; [3:1]: inputs; hp- solc: high [b, a]_req64#. pci-x ? request for 64-bit transfers. the ic drives this signal to the asserted state while [b, a]_preset# is asserted. io vdd33 low 3-state low low [b, a]_serr#. pci-x ? system error signal. input vdd33 low low [b, a]_stop#. pci-x ? target abort signal. during reset, these signals may be 3-state or they may be driven, based on the requirements of the pci-x ? initialization pattern. io vdd33 see left 3-state low low [b, a]_trdy#. pci-x ? target ready signal. during reset, these signals may be 3-state or they may be driven, based on the requirements of the pci-x ? initialization pattern. io vdd33 see left 3-state low low hpsic. hot plug serial input clock; see section 4.5.3.3 for details. this signal is an input only while pwrok is low and an output at all other times. as an input, it is used to specify the default state of deva:0x40[hpsss#]. hpsss# specifies if the ic supports a single hot plug slot on the bridge without external isolation switches. a weak resistor should be tied from this signal to vdd33 or to ground. io (see left) vdd33 high high high high hpsil#. hot plug serial input load; see section 4.5.3.3 for details. this signal is an input while pwrok is low and an output at all other times. as an input, it is used to specify if bridge b of the ic is in hot plug mode or not; the latched state is available in deva:0x48[hpenb]. to specify that bridge b is in hot plug mode, a weak resistor to vdd33 should be placed on this signal. to specify that bridge b is not in hot plug mode, a weak pulldown resistor to ground should be placed on this node. when neither bridge a nor b are in hot plug mode, this signal is always driven high. io (see left) vdd33 high high high high hpsoc. hot plug serial output clock; see section 4.5.3.3 for details. output vdd33 high high high high pin name and description io cell type power plane normal single slot hp during reset after reset during reset after reset
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 12 if a bridge is to be left unused, the signals associated with that bridge should be connected as follows: ? the following signals do not require any connection: [b, a]_ad[63:0], [b, a]_cbe_l[7:0], [b, a]_par, [b, a]_par64, [b, a]_pclk[4:0], [b, a]_preset#. ? the following signals should be tied high through resistors: [b, a]_ack64#, [b, a]_devsel#, [b, a]_frame#, [b, a]_irdy#, [b, a]_perr#, [b, a]_pirq[d:a]#, [b, a]_req[4:0]#, [b, a]_serr#, [b, a]_stop#, [b, a]_trdy#, [b, a]_gnt[4:0]#, [b, a]_pme#, [b, a]_req64#. ? the following signals should be grounded: [b, a]_pcixcap, [b, a]_m66en. ? [b, a]_pllclko should be connected to [b, a]_pllclki. 3.4 test and miscellaneous signals hpsod. hot plug serial output data; see section 4.5.3.3 for details. this signal is an input while pwrok is low and an output at all other times. as an input, it is used to specify if bridge a of the ic is in hot plug mode or not; the latched state is available in deva:0x48[hpena]. to specify that bridge a is in hot plug mode, a weak resistor to vdd33 should be placed on this signal. to specify that bridge a is not in hot plug mode, a weak pulldown resistor to ground should be placed on this node. when neither bridge a nor b are in hot plug mode, this signal is always driven low. io (see left) vdd33 low high low high nioairq[a, b, c, d]#. non-ioapic interrupt requests. each of these signals require a weak pullup resistor to vdd33. in particular, if the state of nioairqc# is low during the rising edge of pwrok, then the ic will enter a production test mode that results in undefined behavior in [b, a]_pllclko and [b, a]_pllclki. see section 4.5.2 and dev[b, a]:0x40[nioamode] for details about the function of these pins. od vdd33 3-state 3-state 3-state 3-state p_cal, p_cal#. pci-x ? phy calibration pins. these are designed for the following external circuit: p_cal should be connected through a resistor to ground; p_cal# should be conneced through a resistor to vdd33. the calculated calibration values associated with these resistors are provided deva:0x[54, 50][calccomp]. input vdd33 pin name and description io cell type power plane during reset after reset cmpovr. link automatic compensation override. 0=link automatic compensation is enabled. 1=the compensation values stored in deva:0x[e0, e4, e8] control the compensation circuit. the state of this signal determines the default value for deva:0x[e0, e4, e8][actl and bctl] at the rising edge of pwrok. input vdd33 free[22:1]. these pins should be left unconnected. ldtstop#. link disconnect control signal. this pin is also used for test-mode selection; see section 9. input vdd33 nc[3:0]. these pins should be left unconnected. pin name and description io cell type power plane normal single slot hp during reset after reset during reset after reset
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 13 pwrok. power ok. 1=all power planes are valid. the rising edge of this signal is deglitched; it is not observed internally until it is high for more than 6 consecutive refclk cycles. see section 4.2 for more details about this signal. input vdd33 refclk. 66 mhz reference clock. this is required to be operational and valid for a minimum of 200 microseconds prior to the rising edge of pwrok and always while pwrok is high. input vdd33 reset#. reset input. see section 4.2 for details. note: reset# is also used as the hot plug [b, a]_hpsor# reset. when reset# is asserted, the hot plug shift register and control latches are reset. input vdd33 rsvd[22:0]. these pins should be left unconnected. strapl[3:2]. strapping options to be tied low. these pins should be tied to ground. input vdd33 test. this pin is required to be tied low for functional operation. see section 9 for details. input vdd33
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 14 3.5 power and ground vdd12[b, a]. 1.2 volt power plane for the hypertransport technology pins. vdd12a provides power to the a side of the tunnel. vdd12b provides power to the b side of the tunnel. vdd18. 1.8-volt power plane for the core of the ic. vdda18. analog 1.8-volt power plane for the plls in the core of the ic. this power plane is required to be filtered from digital noise. vdd33. 3.3-volt power plane for io. vss. ground. 3.5.1 power plane sequencing the following are power plane requirements that may imply power supply sequencing requirements. ? vdd33 is required to always be higher than vdd18, vdda18, and vdd12[b, a]. ? vdd18 and vdda18 are required to always be higher than vdd12[b, a]. 4 functional operation 4.1 overview the ic connects to the host through either the side a or side b hypertransport tm link interface. the other side of the tunnel may or may not be connected to another device. host-initiated transactions that do not target the ic or the bridge flow through the tunnel to the downstream device. transactions claimed by the device are passed to internal registers or to one of the pci-x ? bridges. see section 5.1 for details about the software view of the ic. see section 5.1.2 for a description of the register naming convention. see the amd-8131 tm hypertransport tm pci-x ? tunnel design guide for additional information. 4.2 reset and initialization reset# and pwrok are both required to be low while the power planes to the ic are invalid and for at least 1 millisecond after the power planes are valid. deassertion of pwrok is referred to as a cold reset . after pwrok is brought high, reset# is required to stay low for at least 1 additional millisecond. after reset# is brought high, the links go through the initialization sequence. after a cold reset, the ic can be reset by asserting reset# while pwrok remains high. this is referred to as a warm reset . reset# must be asserted for no less than 1 millisecond during a warm reset.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 15 4.2.1 non-hot plug initialization the operational mode (conventional pci or pci-x) and frequency of the pci-x bridges ([b, a]_pclk[4:0]) are determined after a cold reset by the [b, a]_pcixcap signals, the [b, a]_m66en signals, and by strapping resistors on [b, a]_gnt[4:3] (the a_ signals specify bridge a and the b_ signals specify bridge b). for [b, a]_gnt[4:3], to select a 1, a pullup resistor to vdd33 is placed on the signal; to select a 0, a pulldown resis- tor to ground is placed on the signal. the mode and frequency is determined while pwrok is low and held after pwrok goes high. the options and associated selects are: notes to the above table: ? x means that the state does not matter to the ic. ? the gnt[4:3]# column shows the value latched by the ic while pwrok is low. ? the pcixcap column indicates how the ic observes pcixcap. grounded indicates pcixcap is tied to ground. middle voltage indicates pcixcap is tied to a pullup resistor to vdd33 and between 1 and 5 paral- lel pulldown resisters to ground; these pulldown resistors may come from the systemboard and from cards located in up to four slots. pullup to vdd33 indicates pcixcap is tied to a pullup resistor to vdd33 and no pulldown resistors. ? the supported r/g/p column indicates the sets of req#, gnt#, and pclk signals that are supported by the ics bridge in that mode (there may be other constraints such as electrical requirements that further limit the number of external devices supported). ? if a bridge from the ic supports 5 slots, then only 33 mhz conventional pci mode is supported. in this situ- ation, m66en and pcixcap should be grounded on the systemboard to the slots so that all pci cards prop- erly initialize. ? the state of the straps is reflected in dev[b, a]:0xa0[scf] and dev[b, a]:0x40[cpci66] after a cold reset. ? if the systemboard supports pci-x mode operation for a bridge, then a pullup resistor to vdd33 must be placed on the bridges pcixcap pin. to limit the frequency of a pci-x-capable bridge to 66 mhz on a sys- temboard, the systemboard must also include a pulldown resistor from the bridges pcixcap pin to ground. the strapping options on gnt[4:3]# are used to distinguish between systems that support 100mhz and 133 mhz; in either of these two cases, the system board should include no pulldown resistors on pcixcap. 4.2.2 hot plug initialization bridges in hot plug mode are always placed into 33 mhz, conventional pci mode after reset# is asserted. the operational speed and mode are then initialized by software through the following steps: (1) initialization of write once registers in the shpc[b, a]:xx register block, (2) optional execution of power only all slots shpc command, (3) acquisition of the capabilities and presence information for each slot by observing the rst#, m66en, pcixcap, prsnt1#, and prsnt2# signals, (4) determination of the highest common bus frequency and mode that may be selected, (5) execution of set bus segment speed/mode shpc command for the selected speed and mode, and (6) execution of enable all slots shpc command. this sequence is the same when hot plug single-slot support is selected (dev[b, a]:0x40[hpsss#]). however, gnt[4:3]# pcixcap m66en mode frequency supported r/g/p xxb grounded 0 conventional pci 33.33 mhz [4:0] xxb grounded 1 conventional pci 66.67 mhz [3:0] xxb middle voltage x pci-x ? 66.67 mhz [3:0] 01b pullup to vdd33 x pci-x ? 100.00 mhz [3:0] 00b pullup to vdd33 x pci-x ? 133.33 mhz [2:0]
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 16 all of the slot signals are forced low until the slot is powered. 4.3 clocking it is required that refclk be valid in order for the ic to operate. also, the lr[b, a]clk inputs from the operation links must also be valid at the frequency defined deva:0xcc[freqa] and deva:0xd0[freqb]. the ic provides [b, a]_pclk[4:0] as the clocks to the secondary bus devices. 4.3.1 systemboard requirements the ic provides the pci clocks for secondary-bus devices, [b, a]_pclk[4:0], and a pll feedback for itself, [b, a]_pllclko to [b, a]_pllclki. [b, a]_pllclko is fixed at 66 mhz while [b, a]_pclk[4:0] var- ies based on the specified secondary-bus frequency. the systemboard is required to include a loopback connection from [b, a]_pllclko to [b, a]_pllclki. the length of this connection is required to be approximately the same as the length of the [b, a]_pclk traces from the ic to the external pci devices (the length of the connection from a_pllclko to a_pllclki should be the same as the length of the a_pclk signals and the length of the connection from b_pllclko to b_pllclki should be the same as the length of the b_pclk signals) such that the flight time of the [b, a]_pclk signals is the same as the flight time of the pll feedback. flight time is defined as the time differ- ence between the rising edge of the clock as observed at the source of the systemboard trace ([b, a]_pllclko and [b, a]_ pclk at the ic) and the rising edge of the clock as observed at the destination of the systemboard trace ([b, a]_pllclki at the ic and [b, a]_pclk at the external device), as shown in fig- ure 2. the ic is designed such that, for the purposes of meeting the ic ac timing requirements, if the pclk flight time matches the pll feedback flight time, then pclk as observed at the destination is equivalent to the pci- defined pclk signal to the ic. accordingly, the pll feedback flight time is required to be the same as any of the pclk trace flight times (for a bridge), within the skew limits specified by the pci specifications for pclk to different devices (2 ns for conventional pci 33 mhz; 1 ns for conventional pci 66 mhz; 0.5 ns for all pci- x mode frequencies). to improve the correlation between pclk and the pll feedback flight time, the delay of [b, a]_pllclko and [b, a]_pclk[4:0], relative to each other, may be altered through dev[b, a]:0x40[pclkdel, pllodel]. however, the delay created by each increment of dev[b, a]:0x40[pclkdel and pllodel] varies from device to device. therefore, deva:0x48[bdcv] provides the approximate time differential for each increment of dev[b, a]:0x40[pclkdel and pllodel] on a given device. thus, the values pro- grammed into dev[b, a]:0x40[pclkdel and pllodel] should be determined using deva:0x48[bdcv] to adjust timing on a platform as follows: ? if the pll feedback flight time is greater than the pclk flight time by n picoseconds, then dev[b, a]:0x40[pclkdel] should be set to: n / (1250 / deva:0x48[bdcv]). ? if the pll feedback flight time is less than the pclk flight time by n picoseconds, then dev[b, a]:0x40[pllodel] should be set to: n / (1250 / deva:0x48[bdcv]). the result of the above equations should be rounded to the nearest integer for best accuracy. note that only one of dev[b, a]:0x40[pclkdel] or dev[b, a]:0x40[pllodel] should be set to a value other than zero, never both.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 17 the pclk flight time may vary with different [b, a]_pclk frequencies (this may be a consequence of imper- fect signal integrity of [b, a]_pclk). these differences in flight time may be accounted for on a platform by: (1) for each supported [b, a]_pclk frequency, determine the different time adjustment values required, and (2) use system bios to program dev[b, a]:0x40[pclkdel and pllodel] to correct by these time adjust- ment values based on the [b, a]_pclk frequency and deva:0x48[bdcv]. 4.3.2 characterization for the purposes of characterization, there is no pci-defined pclk signal into the ic, such as is typically used to measure setup, hold, and output valid delay times of pci-bus signals. as shown in figure 2, there is an unspecified skew between the pclk outputs and pllclko (delay x). because of this, along with the fact that the pll feedback frequency may not be the same as pclk, the pll feedback signal cannot be used to characterize the ic pci bus signals. instead, the ic should be characterized as follows: ? make sure dev[b, a]:0x40[pclkdel and pllodel] = 0h. ? measure the pll feedback flight time, pllft, and the flight time of a [b, a]_pclk signal connected to an external device, pclkft. algebraically calculate the difference as follows: difft = pllft - pclkft. note that difft may be a positive or a negative value. ? characterize the pci-bus signals using, as a reference clock, the destination of the [b, a]_pclk used to cal- culate pclkft. then, adjust the measurements to obtain the correct values as follows: ? output valid delay . algebraically subtract difft from the measured output valid delay time of pci bus signals driving out of the ic. corrected output valid delay = measured output valid delay - difft. ? setup . algebraically add difft to the measured setup time of pci bus signals being driven into the ic. corrected setup time = measured setup time + difft. ? hold . algebraically subtract difft from the measured hold time of pci bus signals being driven into the ic. corrected hold time = measured hold time - difft. figure 2: systemboard clocking. a bridge of the ic external pci device dev[b, a]:0x40 [pllodel] dev[b, a]:0x40 [pclkdel] pll and clock tree incoming flops outgoing flops pclk source pllclko pllclki q d pll feedback flight time all pci bus signals pll refclk pclk flight time delay x delay x pclk dest.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 18 4.3.3 clock gating internal clocks may be disabled during power-managed system states such as power-on suspend. it is required that all upstream requests initiated by the ic be suspended while in this state. to enable clock gating, deva:0xf0[icgsmaf] is programmed to the values in which clock gating will be enabled. stop grant cycles and stpclk deassertion link broadcasts interact to define the window in which the ic is enabled for clock gating during ldtstop# assertions. the system is placed into power managed states by steps that include a broadcast over the links of the stop grant cycle that includes the system management action field (smaf) followed by the assertion of ldtstop#. when the ic detects the stop grant broadcast which is enabled for clock gating, it enables clock gating for the next assertion of ldtstop#. while exiting the power-managed state, the system is required to broadcast a stpclk deassertion message. the ic uses this message to disable clock gating during ldtstop# assertions. this is important because an ldtstop# asser- tion is not guaranteed to occur after the stop grant broadcast is received. the clock gating window must be closed to ensure that clock gating does not occur during stop grant for ldtstop# assertions that are not associated with the power states specified by deva:0xf0[icgsmaf]. in summary, stop grant broadcasts with smaf fields specified by deva:0xf0[icgsmaf] enable the clock gating window and stpclk deassertion broadcasts disable the window. if ldtstop# is asserted while the clock gating window is enabled, then clock gating occurs. it is expected that clock gating is only employed during power-on suspend. therefore, os and driver software ensure that no dma or interrupt activity occurs. in addition, it is required that there be no host accesses to the bridges or internal registers in progress from the time that ldtstop# is asserted for clock gating until the link reconnects after ldtstop# is deasserted. figure 3: correction for characterization. pclk (observed at the destination) adjusted pclk (corrected for difference in flight time) difference in pclk and pll feedback flight time, difft output valid delay measurement measured output valid delay corrected output valid delay setup and hold time measurement measured hold time corrected hold time measured setup time corrected setup time
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 19 4.4 tunnel links each hypertransport link supports clk receive and transmit frequencies of 200, 400, 600, 800 mhz. the side a and side b frequencies are independent of each other. 4.4.1 link phy the phy includes automatic compensation circuitry and a software override mechanism, as specified by deva:0x[e8, e4, e0]. the ic only implements synchronous mode clock forwarding fifos. so only the link receive and transmit frequencies specified in deva:0x[d0, cc][freqb, freqa] are allowed. 4.5 pci-x ? bridges the ic includes two 64-bit pci-x bridges, bridge a and bridge b. each independently support pci-x mode or conventional pci mode, clocks speeds of 33, 66, 100, and 133 mhz, and shpc-compatible hot plug. each include an ioapic register set. each support 64-bit addressing in pci-x and legacy pci modes. 4.5.1 tags, unitids, seqids and ordering the ic requires two hypertransport technology-defined unitids. the first unitid applies to bridge a and the second unitid applies to bridge b. it is contained in the following transactions: ? external master requests associated with the bridge. ? ioapic interrupt requests associated with the bridge. ? responses to host-initiated requests that enter the address space of the bridge including configuration regis- ters (deva registers for bridge a and devb registers for bridge b), io and memory space windows defined in the configuration registers of the bridge, and the base address register spaces defined by the bridge. in addition, the unitid associated with the bridge is returned in the response to upstream requests and is used to determine the destination of the response (bridge a or bridge b). the assigned srctag value increments with each non-posted request from 0 to 28 and then rolls over to 0 again; the first srctag assigned after reset is 0. up to 29 non-posted requests to the link may be outstanding at a time per bridge. based on the state of dev[b, a]:0x40[nzseqid], the ic may or may not generate a non-zero seqid values in the upstream link requests that result from external pci master read requests. all bridge-sourced transactions are compliant to pci ordering rules. as pci transactions are converted to link transactions, they are translated as described in the link specification. downstream non-posted link requests to a bridge that contain non-zero seqid values are required to complete on that bus prior to initiating subsequent non-posted requests to that bus with the same seqid value. thus, only one downstream non-posted request with each non-zero seqid value can be outstanding to a bridge at a time. 4.5.2 interrupt controllers each bridge supports the four pci-defined interrupt signals, [b, a]_pirq[d, c, b, a]#. assertion of these interrupt signals may be converted to link interrupt request messages as specified by the ioapic register space. also, the interrupts from both bridges may be combined and output to the respective nioairq[d, c, b, a]# pins, based on dev[b, a]:0x40[nioamode].
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 20 it is expected that system bios sets both dev[b, a]:0x40[nioamode] bits and that the interrupt type is determined by the way the operating system programs the interrupt mask bit (rdr[im]; see section 5.4) of the redirection registers (non-ioapic-capable operating systems set the mask bits resulting in nioairq[d:a]# signal assertions; ioapic-capable operating systems clear the mask bits resulting in interrupt request mes- sages to the host). the nioairq[d:a]# signals from all instances of the ic on a platform may be connected together (respectively: a to a, b to b, etc.). these four nodes are expected to be passed to the systems legacy interrupt controller to generate interrupts on behalf of the ics bridges when ioapic interrupts are not sup- ported. there is a set of ioapic registers associated with each bridge. they include a standard pci function header (function 1 of each bridge) and memory mapped registers. in addition, expanded programmability of these reg- isters is included in dev[b, a]:0x[bc, b8]. the ioapic registers specify the conversion of pirq pin asser- tions to link interrupt request messages. typically, for pci interrupts, the redirection register (rdr; see section 5.4) is set up as follows: mt=fixed; dm=physical mode; pol=active low; tm=level sensitive; and im=not masked. the rdr fields are mapped into link interrupt request messages as follows: rdr field field in link packet iv[7:0] (interrupt vector)vector (bit time 5) mt[2:0] (message type) mt[2:0] (bits[4:2] of bit time 3); mt[3] (bit[7] of bit time 3) should always be low; note that the encoding of these bits changes between the value in the rdr and the value placed into the link packet. dm (destination mode)dm (bit[6] of bit time 3) tm (trigger mode)rqeoi (bit[5] of bit time 3) dest[7:0] (destination)intrinfo[15:8] (bit time 4); intrinfo[55:16] should always be low. ds, pol, irr, and im from the rdr are not included in the link interrupt packet. the state of passpw and intrinfo[55:24, 7] from the idrdr register (see dev[b, a]:0x[bc, b8]) are also passed along in the link interrupt packet. if rdr[tm]=level sensitive for the interrupt request, then the irr register is set when the interrupt is detected. after the interrupt request message is sent to the host, the host is required to generate an eoi broadcast mes- sage when finished with that interrupt. irr is cleared in any rdrs (in either bridge) with idrdr/rdr fields that match the intrinfo fields of the eoi broadcast as follows: intrinfo[15:8] match fields 00h intrinfo[31:16] = {idrdr[31:24], rdr/idrdr[iv]}; 01h-ffh intrinfo[31:8] = {idrdr[31:24], rdr/idrdr[iv], rdr/idrdr[dest]}; if the interrupt signal is still asserted when the corresponding rdr logic receives an irr-clearing eoi, then irr is set again immediately and a new interrupt request message is sent. if the interrupt signal is deasserted near the time the corresponding irr-clearing eoi is received, then it is undefined whether an additional inter- rupt request message is sent. if rdr[tm]=edge sensitive, then the state of the irr bit is not specified and the rdr logic for that interrupt does not observe eois. each rdr in the ic operates independently. if interrupts are received simultaneously by two rdr controllers, then the corresponding interrupt request messages from each are transmitted in an unspecified order.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 21 if ldtstop# is asserted near the time that an interrupt is asserted, then the corresponding interrupt request message may or may not be sent before the disconnect sequence completes. if it is not sent before the discon- nect sequence completes, then it is not dropped; it is sent after the link is re-connected. external devices are required to assert pirq[d:a]# for at least 3 pclk cycles in order to guarantee that the ic detects the assertion, regardless of the state of the corresponding rdr[tm] field. 4.5.2.1 error nmi interrupts nmi interrupts may be generated as a result of assertions of the [b, a]_perr# and [b, a]_serr# signals (regardless of the source of the assertion), as enabled by dev[b, a]:0x44[nmien]. these interrupt requests are generated with the following link format: passpw=0; intrinfo[55:24]=0000_00f8h; iv=00h; dest=ffh; dm=0 (physical); tm=0 (edge); mt=0011b (nmi). 4.5.3 hot plug each pci-x bridge includes an shpc-compliant hot plug controller that may be used to support hot plug capa- ble conventional pci or pci-x slots. strapping options on hpsod and hpsil# specify if hot plug is sup- ported on bridge a and/or b. if hot plug is supported on a bridge, then all slots connected to that bridge are required to include hot plug support circuitry. with the exception of a single-slot hot plug implementation, the hot plug support circuitry includes one or more texas instruments tps2340 hot plug power controllers, power switches, and associated slot isolation switches to provide electrical isolation for most of the slot signals. for a single-slot hot plug implementation, the ic provides the bus isolation function; therefore only the ti tps2340 hot plug power controller and the power switches are required. each bridge supports a maximum of 4 slots when hot plug mode is enabled. the ics hot plug controller is designed to interface with the ti tps2340 hot plug power controller. each ti tps2340 controls two slots and provides two separate sets of isolation switch controls. ti tps2340 controllers may be cascaded to support additional slots. a single ti tps2340 hot plug power controller cannot be shared across bridge a and bridge b. the ic is connected to the power controller via a serial bus. one serial interface supports the power controllers for bridge a and bridge b. 4.5.3.1 multi-slot hot plug if multiple hot plug slots are supported on a bridge, isolation switches are required for each slot to provide electrical isolation. each ti tps2340 hot plug power controller provides two pairs of isolation switch control signals, busenx# and clkenx#, to control the state of the switches.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 22 the following table associates the hot plug power controllers isolation switch control signal with the ics slot signals. the ti tps2340 hot plug power controller controls reset# to the slot. the ics [b, a]_preset# signals are connected to the ti tps2340 hot plug power controllers serial interface control signal, sorr#. some operating systems require that each configuration-space bus number provide a separate pme# signal to a general-purpose set of pme# status bits provided by the platform system management logic. the ics [b, a]_pme# signals are associated with the power management configuration registers dev[b, a]:0x[9c:98], both of which are observed by software on the primary side of the pci bridges and are therefore on the same bus number. therefore, the ics two [b, a]_pme# pins may be connected together and passed to the platform system management logic. the slots are observed by software on the ics secondary bus, which is a different bus number from the pri- mary side. therefore, the each bridge should provide a separate pme# signal to the platform system manage- ment logic, that logically connects to all the slots behind the bridge. the ti tps2340 hot plug power controllers pme# inputs connects to the pme# signal of each hot plug slot. its pme# outputs for one bridge should be connected together and passed to the platform system management logic. figure 4: system diagram for multiple hot plug slots on a bridge. power controller signal slot signals isolated busenx# [b, a]_ack64#, [b, a]_ad[63:0], [b, a]_cbe_l[7:0], [b, a]_devsel#, [b, a]_frame#, [b, a]_gnt#[3:0], [b, a]_irdy#, [b, a]_par, [b, a]_par64, [b, a]_perr#, [b, a]_pirq[a, b, c, d]#, [b, a]_req#[3:0], [b, a]_req64#, [b, a]_serr#, [b, a]_stop#, [b, a]_trdy#. clkenx# [b, a]_pclk[3:0], [b, a]_m66en. table 2. signal isolation groups. power controllers hot plug serial bus controller link link a b pci-x ? pci-x ? shpc shpc a b 1234 pcix pcix power and isolation control 1234 - isolation switch bridge a bridge b
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 23 the slot signals that are used to communicate the speed, capability (m66en and pcixcap), and presence of an adapter card (prsnt[1:2]#) are isolated from the other slots in a hot plug implementation. these signals are directly connected from the slot connector to their associated ti tps2340. the state of these signals is pro- vided to the ic through the serial interface. the ic, in turn, makes the state of these signals available to system software. the [b, a]_pcixcap and [b, a]_m66en pins on the ic are not used for sensing speed and mode. the ics [b, a]_pcixcap pins are left unconnected. the connection and function of the m66en signal is unique in a hot plug implementation for two reasons: (1) m66en is driven as an output of the ic; (2) its isolation switch control is driven by clken# rather than busen# (unlike other pci/pci-x control signals). in a hot plug configuration, the ics [b, a]_m66en pin is configured as an open-drain output. it is driven low by the ic if it is determined that the bus is to run at 33mhz (conventional pci mode), as indicated in shpc[b, a]:x10[mode]. figure 5: system diagram of pme# signals. figure 6: system diagram of m66en signals. a_pme# bridge a, slot (n) power controller pme#(n) the ic 3.3va pmeo# pmeo# power controller platform system bridge pme# management logic bridge a, slot (n+1) pme#(n+1) bridge a, slot (n+2) pme#(n+2) bridge a, slot (n+3) pme#(n+3) 3.3v b_pme# [b, a]_m66en - isolation switch slot (n) power controller m66en(n) the ic 3.3v slot power slot (n+1) m66en(n+1) 3.3v slot power clken(n)# clken(n+1)#
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 24 the process of setting the state of [b, a]_m66en when the bridge is initialized is: (1) the ti tps2340 hot plug power controller is programmed to apply power to the slots via the shpc[b, a]:14 power-only all slots com- mand; (2) software observes the state of the speed capability signals for the slots by reading shpc[b, a]:[30:24][m66_cap]; (3) software issues the shpc[b, a]:14 set bus segment speed/mode command, which immediately places the appropriate state on [b, a]_m66en out of the ic; (4) software issues the shpc[b, a]:14 slot enable command, which results in the assertion of clkenx# so that [b, a]_m66en out of the ic is enabled to the slot. 4.5.3.2 single-slot hot plug isolation switches are not required if the bridge supports a single hot plug slot. the ic provides the isolation function by controlling the slot signals appropriately. the ti tps2340 hot plug power controller is still required. figure 7: multi-slot hot plug enable/disable sequence. [b, a]_preset# pwren clkenx# busenx# most slot signals valid [b, a]_pclk[3:0] valid slot power slot enable command sequence slot disable command sequence ? signal states are shown from the perspective of the pins of the ic; the perspective from the slot is different due to the isol ation switches controlled by clkenx# and busenx#. ? most slot signals includes the signals controlled by busenx#. ? m66en is driven low after reset# is asserted; after that, its state is determined by the bus speed and mode. 120-150 ms 60-90 ms slot reset# 6-10 us 6-10 us about 22 pclk cycles about 22 pclk cycles
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 25 single-slot hot plug support is enabled for each bridge through strapping options on hpsic and b_gnt2#. the state of these strapping options are observable through dev[b, a]:0x40[hpsss#]. the ic drives all slot signals low throughout the duration of a cold reset and continues to do so until after the ti tps2340 hot plug power controller applies power to the adapter. the ic interprets the shpc commands to control the signals in the power-only, slot enable, and slot disable sequences. the following figure shows how signals are controlled by the ic during the sequence initiated by the slot enable command and the slot disable command. figure 8: single-slot hot plug system diagram. power controller hot plug serial bus controller link link a b pci-x ? pci-x ? shpc shpc a b pcix pcix power controller bridge a bridge b
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 26 the ics [b, a]_pcixcap pins are left unconnected. pcixcap and prsnt[1:2]# from the slot are con- nected to the ti tps2340 hot plug power controller. the ics [b, a]_m66en pins are connected directly to the slot with a pull-up resistor to the slot power plane. this pin remains tri-stated until the shpc enables the slot so the state provided by the card in the slot may be observed. this pin is driven low by the ic if it is determined that the bus is to run at 33mhz in conventional pci mode. figure 9: single-slot hot plug enable/disable sequence. figure 10: single-slot hot plug m66en connections. [b, a]_preset# pwren clken busen most slot signals valid [b, a]_pclk0 valid m66en 1 if conventional pci, 66 mhz; otherwise 0 tristate tristate [b, a]_req0# observed as an input tristate; input ignored slot power tristate; input ignored slot enable command sequence slot disable command sequence ? clken and busen represent the approximate times in which the ti tps2340 change the state of its clkenx# and busenx# sig- nals. however, these signals out of the ti tps2340 do not directly control the above signals. ? pwren represents the times in which the ti tps2340 enables power to the slot. ? most slot signals includes the signals controlled by busenx# in section 4.5.3.1. 120-150 ms 60-90 ms slot reset# 6-10 us 6-10 us about 22 pclk cycles about 22 pclk cycles [b, a]_m66en slot (n) power controller m66en(n) the ic slot power
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 27 the process of setting the state of [b, a]_m66en when the bridge is initialized is: (1) the ti tps2340 hot plug power controller applies power to the slot via the shpc[b, a]:14 power-only command; (2) software observes the state of the speed capability signals for the slot by reading shpc[b, a]:[24][m66_cap]; (3) software issues the shpc[b, a]:14 set bus segment speed/mode command which determines the state of [b, a]_m66en (but the state of the pins does not change); (4) software issues the shpc[b, a]:14 slot enable com- mand and [b, a]_m66en may be driven low at the same time that clkenx# is asserted out of the ti tps2340. the ic is designed such that only active-low interrupts (from [b, a]_pirq[d:a]#) are supported when in sin- gle-slot support mode, while the slot is not enabled. if the ioapic is programmed for active high interrupts in this mode, then spurious interrupt requests are generated. 4.5.3.3 serial interface the hot plug serial interface operates at 8.33 mhz. it converts shpc commands to a serial format to commu- nicate with the ti tps2340 hot plug power controllers. in addition, it is used to read status information from the ti tps2340 hot plug power controllers and update the ics shpc status registers accordingly. the follow- ing table identifies two different groups of serial interface signals. common serial signals are connections between the ic and all ti tps2340 hot plug power controllers (shared across both pci/pci-x bridges). bridge specific signals are connections between the ic and only those ti tps2340 hot plug power controllers con- nected to a particular bridge. (for additional information, see ti tps2340a dual-slot pci hot-plug power controller .) figure 11: hot plug serial interface connections. a_hpsorr#, a_hpsolc, a_hpsorlc b_hpsorr#, b_hpsolc, b_hpsorlc hpsic, hpsoc, hpsil# hpsor# = system reset# signal hpsod a_hpsid ti tps2340 the ic sidi sido sodo sodi sidi sido sodo sodi sidi sido sodo sodi sidi sido sodo sodi b_hpsid bridge a slots 1 & 2 ti tps2340 bridge a slots 3 & 4 ti tps2340 bridge b slots 1 & 2 ti tps2340 bridge b slots 3 & 4 reset#
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 28 common serial signals hpsic. output. this 8.33 mhz clock is used to shift serial data from the ti tps2340 to the ic over [b, a]_hpsid. each bit is captured by the ic on the rising edge of this clock. hpsil#. output. this signal is used to specify the start of an input data frame and the data type--or channel number--being shifted into the ic over [b, a]_hpsid. hpsoc. output. this 8.33 mhz clock is use to shift serial data from the ic to the ti tps2340 over hpsod. each bit is captured by the ti tps2340s on the rising edge of this clock. hpsod. output. this is the serial data shifted from the ic to the ti tps2340s, clocked by hpsoc. hpsor#. the ti tps2340s sor# input is connected to the same platform reset signal as is used for the ics reset#. when sor# is asserted, all of the slot control outputs of the ti tps2340 are reset except the slot reset signal, resetx# (which is reset by [b, a]_hpsorr#). bridge specific serial signals [b, a]_hpsid. input (multiplexed with [b, a]_pclk4). this is the serial data shifted into the ic from the ti tps2340s, clocked by hpsic. [b, a]_hpsolc. output (multiplexed with [b, a]_req4#). this signal is used to load the state of the serial data shifted into the ti tps2340 over hpsod into output latches. all outputs of the ti tps2340 are updated on the rising edge of [b, a]_hpsolc, except the slot reset signal, resetx# (which is updated by [b, a]_hpsorlc). [b, a]_hpsorlc. output (multiplexed with [b, a]_gnt4#). this signal is used to load the state of the slot reset signals shifted into the ti tps2340 over hpsod into output latches. resetx# out of the ti tps2340 is updated on the rising edge of [b, a]_hpsorlc. [b, a]_hpsorr#. output (multiplexed with [b, a]_preset#). this signal is used to reset the state of the ti tps2340s output latches that drive resetx# (to low). 4.5.3.3.1 serial data from the power controllers to the ic channel 00b interrupt-capable data and channel 01b non-interrupt-capable data is shifted into the ic from the ti tps2340 over [b, a]_hpsid using hpsic as the clock. this data is continuously shifted into the ic, tog- gling between channels 00b and 01b. hpsil# controls the start of each block and specifies the channel num- ber. hpsil# transitions after the falling edge of hpsic. the tables below show how the data for 4 slots are transferred into the ic. however, the actual number of slots transferred is limited to the maximum of the num- ber of slots on bridge a or bridge b. clock # hpsil# data out of ti tps2340 over [b, a]_hpsid after rising edge of hpsic 01 10 (start) 2 0 (chan[0]) 3 0 (chan[1]) 41 5 1 first tps2340 swa signal (1=mrl sensor is open) passed to shpc[b, a]:24[mrls]. 6 1 first tps2340 buttona# signal (1=attention button is being pressed; this is an inversion of the state as it is placed onto the tps2340 buttona# pin) passed to shpc[b, a]:24[ab]. 7 1 first tps2340 power fault state (0=power fault is detected) passed through an inverter to shpc[b, a]:24[pf]. 8 1 first tps2340 prsnt2a# signal passed to shpc[b, a]:24[prsnt1_2]. table 3: channel 00b, interrupt capable serial hot plug data to the ic.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 29 4.5.3.3.2 serial data from the ic to the power controllers serial data is transferred over hpsod to the ti tps2340s, where it is stored, using hpsoc as the clock. the state of the outputs and control signals stored in the power controller do not change until a rising edge of [b, a]_hpsorlc, in the case of resetx#, and [b, a]hpsolc, in the case of the rest of the signals. the data is shifted whenever there is a need to change the state of these signals, normally as a result of a command to shpc[b, a]:14. the ic shifts out four slots worth of data, regardless of how many slots are actually attached to the bridge, followed by pulses on [b, a]_hpsorlc and [b, a]hpsolc. hpsod transitions after the fall- ing edge of hpsoc. 9 1 first tps2340 prsnt1a# signal passed to shpc[b, a]:24[prsnt1_2]. 12:10 1 reserved. 17:13 1 first tps2340 slot b signals passed to shpc[b, a]:28[prsnt1_2, pf, ab, mrls]. 20:18 1 reserved. 25:21 1 second tps2340 slot a signals passed to shpc[b, a]:2c[prsnt1_2, pf, ab, mrls]. 28:26 1 reserved. 33:29 1 second tps2340 slot b signals passed to shpc[b, a]:30[prsnt1_2, pf, ab, mrls]. clock # hpsil# data out of ti tps2340 over [b, a]_hpsid after rising edge of hpsic 10 (start) 2 1 (chan[0]) 3 0 (chan[1]) 41 5 1 first tps2340 m66ena signal passed to shpc[b, a]:24[m66_cap]. 6 1 first tps2340 pcixcapa# signal passed to shpc[b, a]:24[pcix_cap]. 7 1 first tps2340 pcixcapa# signal passed to shpc[b, a]:24[pcix_cap]. 8 1 first tps2340 auxiliary power fault state (not observable). 12:9 1 reserved. 16:13 1 first tps2340 slot b signals passed to shpc[b, a]:28[m66_cap, pcix_cap]. 20:17 1 reserved. 24:21 1 second tps2340 slot a signals passed to shpc[b, a]:2c[m66_cap, pcix_cap]. 28:25 1 reserved. 32:29 1 second tps2340 slot b signals passed to shpc[b, a]:30[m66_cap, pcix_cap]. table 4: channel 01b, non-interrupt capable serial hot plug data to the ic. clock # data out of the ic over hpsod during the rising edge of hpsoc 1 second tps2340 slot b power enable state. 1=power enabled to the slot. 2 second tps2340 clkenb state. 1=clken signals enabled. 3 second tps2340 busenb state. 1=busen signals enabled. 4 second tps2340 resetb# state. 5 second tps2340 pwrledb# state. 1=turn on power led. table 5: serial hot plug data from the ic to the power controller. table 3: channel 00b, interrupt capable serial hot plug data to the ic.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 30 4.5.3.4 shpc interrupts, events, and errors under the conditions described by shpc[b, a]:20, the ic may assert [b, a]_pirqa#, [b, a]_pme#, or indi- cate a system error on the links. 4.5.3.5 reset to hot plug slots the state of reset for each hot plug slot is passed from the shpc controller, through the serial bus, to the ti tps2340 hot plug power controllers, where it is driven to the slots. the pci requirement for a delay between the rising edge of rst# and the first configuration access is not enforced by the ic with hardware; it is expected that this requirement be enforced through software. the hot plug software driver may be used to inhibit configuration accesses to a slot after commands that result in deassertions of rst# to the slot are executed. the set bus speed/mode command and the enable slot com- mand result deassertions of rst#. each of these commands complete in less than 250 milliseconds after being received by the ic. the pci requirement results in a 0.5 to 1.0 second period (depending on the bus frequency) after the deassertion of rst# during which configuration accesses to the slot are not allowed. therefore, if the hot plug driver inhibits configuration accesses to the slot for 1.25 seconds after these commands are sent to the ic, the pci requirement should be satisfied. 4.5.4 pci-x ? phy compensation update the pci-x phy calculated compensation values may change at any time. these may be altered, based on deva:0x[54, 50], before being passed on to the phy. the ic ensures that the pci-x bridges are idle when new values are passed to the phy. the following logic is implemented to accomplish this: ? shortly after reset, or whenever a new value is written to deva:0x[54, 50], and every 16 milliseconds there- after, the ic determines if any of the values that are to be present to the phy have changed and therefore need to be updated. if the values have not changed, no action takes place until the next 16 millisecond period passes and the values are checked again. ? if the compensation values are to be updated, then the logic request control over the bridges for the compen- sation update. ? the logic ensures that the bridges are idle for at least two pclk cycles before and 4 pclk cycles after the new values are passed to the phy. during these six or more pclk cycles, the ic drives the value of 0123_4567_89ab_cdefh onto [b, a]_ad[63:0]. 6 second tps2340 attledb# state. 1=turn on attention led. 8:7 reserved. 14:9 second tps2340 slot a control signals and outputs. 16:15 reserved. 22:17 first tps2340 slot b control signals and outputs. 24:23 reserved. 30:25 first tps2340 slot a control signals and outputs. table 5: serial hot plug data from the ic to the power controller.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 31 4.5.5 transactions claimed by the bridges the bridges claim no upstream transactions. they claim the following downstream transactions: ? all memory and io space specified by dev[b, a]:0x[30:1c]. ? all configuration cycles to the implemented functions of deva or devb (see section 5.1.2). ? all configuration cycles to buses behind bridge a and bridge b. ? all eoi broadcasts are passed to the ioapic. ? all stop grant and stpclk broadcasts are observed for clock gating (see section 4.3.3). ? if deva:0x48[compat]=1, then all memory space, io space, and interrupt acknowledge packets in which the compat bit is set are claimed and passed to bridge a. per the link protocol, when the compat bit is set in the transaction and deva:0x48[compat]=0, then the ic never claims the transaction. such transactions are automatically passed to the other side of the tunnel (or master aborted if the ic is at the end of the chain). 4.5.6 various behaviors ? cacheline-wrap mode is not supported. if a transaction is initiated that indicates this protocol, it is discon- nected at the first data phase. ? downstream special cycles that are encoded in configuration cycles to device 31 of the bridges secondary bus number (per the pci-to-pci bridge specification) are translated to special cycles on the bridge. ? secondary-bus configuration cycles are never claimed by the ic (including configuration cycles to device 31 in which special cycles are encoded per the pci-to-pci bridge specification). ? in the translation from type 1 link configuration cycles to secondary bus type 0 configuration cycles, the ic converts the device number to an idsel ad signal as follows: device 0 maps to ad[16]; device 1 maps to ad[17]; and so forth. device numbers 16 through 31 are not valid. ? transactions that cross address space boundaries, as defined by the window configuration registers, dev[b, a]:0x[30:1c], result in undefined behavior. ? if the bridge is in pci-x mode and an upstream memory read or write request is issued with the no snoop bit of the attribute field set high, then the coherent bit of the corresponding link read sized or write sized requests is low. the coherent bit is high for all other link requests, including all conventional pci transactions and io commands. the no snoop field bit of the attribute field is always low in downstream requests to the pci-x bridge. ? the following tables show the relationship between pci-x transactions in which the relaxed ordering bit is set and link packets: downstream link transaction corresponding pci-x ? transaction a read request in which bit[3] of the command field (response may pass posted write) is set. relaxed ordering bit of the attribute field is set. a response in which passpw is set. relaxed ordering bit of the attribute field is set. a posted memory write in which the passpw bit is set. no effect; the relaxed ordering bit is zero regardless of the state of the passpw bit.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 32 ? if there is a downstream pci-x request that results in a device-specific error in the completion message, then the response passed to the link indicates a target abort (error bit set; nxa clear). ? when the ic asserts [b, a]_devsel#, it does so using the medium decoding clock in conventional pci mode and the b decoding clock in pci-x mode. ? if there is a link transaction to io-space that targets a bridge and that crosses a naturally aligned dword boundary, then the ic does not send the transaction to the bus and the link response is a master abort (error bit set; nxa set). upstream pci-x ? transaction corresponding link transaction a read request in which the relaxed ordering bit of the attribute field is set. bit[3] of the command field (response may pass posted write) in the read request is set. a split completion in which the relaxed ordering bit of the attribute field is set. passpw is set in the response. an immediate response to a downstream link read request in which bit[3] of the command field (response may pass posted write) is set. passpw is set in the response (even though there is no attribute field associated with the pci-x response). a posted memory write in which the relaxed ordering bit of the attribute field is set. no effect; passpw is zero regardless of the state of the relaxed ordering bit.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 33 4.5.7 error conditions and handling the tables below describe how the ic responds to error conditions. error handling for secondary bus responses to the ic. response from the secondary bus behavior of the ic signal master abort (devsel not asserted); dev[b, a]:0x3c[marsp]=0. ? link response with data of all f's for non-posted transaction. ? posted transaction is discarded. ? dev[b, a]:0x1c[rma]=1. signal master abort (devsel not asserted); dev[b, a]:0x3c[marsp]=1; non-posted request. ? link response with data of all f's and the error bit set. ? dev[b, a]:0x04[sta]=1. ? dev[b, a]:0x1c[rma]=1. signal master abort (devsel not asserted); dev[b, a]:0x3c[marsp]=1; posted request. ? posted transaction is discarded. ? dev[b, a]:0x1c[rma]=1. ? if dev[b, a]:0x04[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? outgoing links are flooded with sync packets. signal master abort (devsel not asserted) for a split completion message to the sec- ondary bus. ? split completion transaction is discarded. ? dev[b, a]:0x1c[rma]=1. ? dev[b, a]:0xa0[scd]=1. ? if dev[b, a]:0x04[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? outgoing links are flooded with sync packets. signal target abort; non-posted request. ? link response with data of all f's and the error bit set. ? dev[b, a]:0x04[sta]=1. ? dev[b, a]:0x1c[rta]=1. signal target abort; posted request. ? remainder of posted transaction is discarded. ? dev[b, a]:0x1c[rta]=1. ? if dev[b, a]:0x04[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? outgoing links are flooded with sync packets. link response with data of all f's and the error bit set. signal target abort for a split completion message to the secondary bus. ? split completion transaction is discarded. ? dev[b, a]:0x1c[rta]=1. ? dev[b, a]:0xa0[scd]=1. ? if dev[b, a]:0x04[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? outgoing links are flooded with sync packets. split completion error; pci-x bridge error; master abort dev[b, a]:0x3c[marsp]=0. ? link response with data of all f's for non-posted transaction. ? dev[b, a]:0x1c[rma]=1. split completion error; pci-x bridge error; master abort dev[b, a]:0x3c[marsp]=1. ? link response with data of all f's and the error bit set. ? dev[b, a]:0x04[sta]=1. ? dev[b, a]:0x1c[rma]=1. split completion error; pci-x bridge error; target abort. ? link response with data of all f's and the error bit set. ? dev[b, a]:0x04[sta]=1. ? dev[b, a]:0x1c[rta]=1.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 34 error handling error conditions detected by the ic. split completion error; pci-x bridge error; write data parity error. ? a targetdone response is returned with no error indicated. ? if dev[b, a]:0x3c[peren]=1, then: ? dev[b, a]:0x1c[mdpe]=1. split completion error; completer error; byte count out of range. ? link response with data of all f's and the error bit set. ? dev[b, a]:0x04[sta]=1. split completion error; completer error; split write data parity error. ? a targetdone response is returned with no error indicated. ? if dev[b, a]:0x3c[peren]=1, then: ? dev[b, a]:0x1c[mdpe]=1. split completion error; completer error; device specific error. ? link response with data of all f's and the error bit set. ? dev[b, a]:0x04[sta]=1. error condition to ic behavior of the ic link response to the bridge indicates a mas- ter abort; pci-x mode. ? split completion indicates a master abort pci-x bridge error. ? dev[b, a]:0x04[rma]=1. link response to the bridge indicates a mas- ter abort; conventional pci mode; dev[b, a]:0x3c[marsp]=0. ? data of all f's is returned. ? dev[b, a]:0x04[rma]=1. link response to the bridge indicates a mas- ter abort; conventional pci mode; dev[b, a]:0x3c[marsp]=1. ? target abort signaled on the pci bus. ? dev[b, a]:0x04[rma]=1. ? dev[b, a]:0x1c[sta]=1. link response to the bridge indicates a tar- get abort in conventional pci mode. ? signal target abort on pci bus; the rest of the data associated with transaction is discarded. ? dev[b, a]:0x04[rta]=1. ? dev[b, a]:0x1c[sta]=1. link response to the bridge indicates a tar- get abort in pci-x mode. ? split completion indicates a target abort pci-x bridge error; the rest of the data associated with the pci-x transaction is dis- carded. ? dev[b, a]:0x04[rta]=1. ? dev[b, a]:0x1c[sta]=1. parity error is detected in address or attribute phase of a transaction from the sec- ondary bus to the ic. ? dev[b, a]:0x1c[dpe]=1. ? if [b, a]:0x3c[peren]=1, then: ? the ic claims the transaction and terminates with a target abort; and ? dev[b, a]:0x1c[sta]=1; and ? if dev[b, a]:0x04[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? both links are flooded with sync packets. parity error detected in the data phase of a split completion message from the second- ary bus to the ic. ? dev[b, a]:0x1c[dpe]=1. ? if [b, a]:0x3c[peren]=1, then: ? the ic claims the transaction and terminated with a target abort; and ? dev[b, a]:0x1c[mdpe]=1; and ? if dev[b, a]:0x04[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? both links are flooded with sync packets.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 35 parity error detected in the data phase of a split completion transaction from the sec- ondary bus to the ic. ? the data is passed to the link as read by the ic. ? dev[b, a]:0x1c[dpe]=1. ? if [b, a]:0x3c[peren]=1, then: ? dev[b, a]:0x1c[mdpe]=1; and ? [b,a] perr# is asserted; and ? if dev[b, a]:0x44[nmien]=1, then: ? nmi is generated. parity error is detected in the data phase of a read response from the secondary bus to the ic. ? the data is passed to the link as read by the ic. ? dev[b, a]:0x1c[dpe]=1. ? if dev[b, a]:0x3c[peren]=1, then: ? dev[b, a]:0x1c[mdpe]=1; and ? [b, a]_perr# is asserted; and ? if dev[b, a]:0x44[nmien]=1, then: ? nmi is generated. [b, a]_perr# is detected asserted after a data phase of a read split completion or read immediate response from the ic to the sec- ondary bus. ? if dev[b, a]:0x44[nmien]=1, then: ? nmi is generated. [b, a]_perr# is detected asserted after the data phase of a non-posted write from the ic to the secondary bus. ? a targetdone response is returned with no error indicated. ? if dev[b, a]:0x3c[peren]=1, then: ? dev[b, a]:0x1c[mdpe]=1. ? if dev[b, a]:0x44[nmien]=1, then: ? nmi is generated. parity error is detected in the data phase of a posted or non-posted write from the second- ary bus to the ic. ? the data is passed to the link as received by the ic. ? dev[b, a]:0x1c[dpe]=1. ? if dev[b, a]:0x3c[peren]=1, then: ? [b, a]_perr# is asserted; and ? if dev[b, a]:0x44[nmien]=1, then: ? nmi is generated. [b, a]_perr# is detected asserted after the data phase of a posted write from the ic to the secondary bus. ? if dev[b, a]:0x3c[peren]=1, then: ? dev[b, a]:0x1c[mdpe]=1; and ? if dev[b, a]:0x04[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? both links are flooded with sync packets. ? if dev[b, a]:0x44[nmien]=1, then: ? nmi is generated. [b, a]_serr# or [b, a]_shpc_serr assertion is detected. ? dev[b, a]:0x1c[rse]=1. ? if both dev[b, a]:0x04[serren]=1 and dev[b, a]:0x3c[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? both links are flooded with sync packets. ? if dev[b, a]:0x44[nmien]=1, then: ? nmi is generated.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 36 link crc error is detected. ? appropriate bit of deva:0x[c8:c4][crcerr]=1. ? if both dev[b, a]:0x04[serren]=1 and deva:0x[c8:c4][crcfen]=1, then: ? dev[b, a]:0x04[sse]=1; and ? outgoing links are flooded with sync packets. link incoming sync flood is detected. ? outgoing links are flooded with sync packets. discard timer time out (only in conven- tional pci mode). ? transaction is thrown out. ? dev[b, a]:0x3c[dts]=1. ? if both dev[b, a]:0x3c[dtse]=1 and dev[b, a]:0x04[serren]=1, then: ? dev[b, a]:0x04[sse]=1; and ? outgoing links are flooded with sync packets. the ic detects an illegal address/byte enable combination during the address phase of a transaction from the secondary bus to the ic. ? the transaction is terminated by signaling a target abort. ? dev[b, a]:0x1c[sta]=1.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 37 4.6 performance-related information 4.6.1 bandwidth percentage one important measure of the ic performance is the ratio of data bandwidth that can pass over the pci bus to the theoretical maximum. this is called the bandwidth percentage or bwp. the theoretical maximum is defined as the product of the bus width and the bus frequency. this does not account for clocks that are required by the protocol for purposes other than data transfer, e.g., address phases. the ic is implemented in such a way that when external pci devices generate long data length transactions, the clocks that are lost to the protocol become less significant to the bwp. if external pci devices generate many small data length transac- tions, then this acts to reduce the bwp. memory read requests and write requests from external pci masters have different bwp characteristics. gen- erally speaking, memory writes are handled with high bwp values because they use the link posted channel. write requests are converted from pci protocol to link protocol by the ic efficiently. memory reads, however, use the link non-posted channel. the response to each read request cannot be provided to the pci bus until it is available. the time required for the response to reach the pci bus includes the time for the request to pass from the pci bus to the ic and from the ic to the host, and for the response to pass from the host back to the ic and from the ic out to the pci bus. if there are other tunnel devices between the ic and the host, these will act to further increase this latency. if, for example, a single pci master generates a pattern of (1) a single-cacheline (64 bytes) memory read request, (2) a burst of the response data to the pci bus, (3) repeat, and that is the only activity on the bus, then the bwp is low; there will be many idle clocks, waiting for the response, between each cacheline burst on the pci bus. bwp may be improved by support for multiple, simultaneous read requests. in conventional pci mode and pci-x mode, the ic supports up to 8 independent pci read requests simultaneously, per bridge. if, as in the example above, two masters generate a pattern of (1) a single-cacheline memory read request, (2) a burst of the response data to the pci bus, (3) repeat, then, the total bwp may roughly double. in pci-x mode, long data length reads result in a high bwp because the time spent transferring data on the pci bus becomes large compared to the time waiting for the response data. in conventional pci mode, the size of the read requests is not provided by the protocol. instead, the memory read command code provides hints as to the amount of data that may be required by the external pci master. dev[b, a]:0x4c specifies the number of cachelines that are prefetched from the host based on the pci com- mand code. the initial prefetch value in this register should be balanced based on the requirements of the sys- tem. if it is too high (such that the master does not use all the data), then unnecessary memory read requests are generated and the corresponding data is thrown out. if it is too low, then the response latency is not well cov- ered, resulting in a low bwp. the logic for each bridge can generate up to 29 link read requests, each request for up to 64 bytes (one cache- line) of data, in support of read commands generated by external pci-bus devices. these link requests are gen- erated by the ic in the order in which they are received from the pci bus. however, the responses to these pci read requests may be provided on the pci bus in a different order from the order in which the requests were received by the ic; this reordering depends on a number of factors including when the data for each request is provided by the host and if the master is ready to accept the data. the following table provides some bandwidth percentages measured in an ideal-model simulation environ- ment. this data is provided for guidance, with no guarantee that it represents the exact behavior of a real-world system design. for these measurements:
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 38 ? all simulations are run while multiple, simultaneous requests are being processed. read measurements are taken on the pci bus, after host latency has passed, such that host latency does not affect the results. ? no other traffic is present except the requests associated with the measurements. ? conventional pci numbers presume that prefetching is enabled in continuous mode and the initial prefetch value is programmed to be high enough to cover the round-trip latency of the response. thus, all cachelines of the response to a request can be burst onto the pci bus without interruption. ? these results apply to all pci-bus frequencies supported by the ic. ? number of cachelines specifies the number of 64-byte cachelines requested by the pci master. note that the overhead is the same, regardless of the number of cachelines requested. ? to ta l c lo c ks specifies the number of clocks from the end of one burst, associated with one request, to the end of the next burst, associated with another request. it is the sum of the burst clocks and overhead clocks. ? overhead clocks specifies the number of pci bus clocks during which there is no data transfer due to pci protocol overhead and overhead inherent to the ic. ? data burst clocks specifies the number of pci bus clocks during which data is transferred. ? bwp is bandwidth percentage. bwp=(burstclks/totalclks)*100. type number of cachelines pci bus width total clocks over- head clocks data burst clocks bwp conventional pci writes to host memory 2 32 bit 37 5 32 86 64 bit 21 5 16 76 8 32 bit 133 5 128 96 64 bit 69 5 64 93 32 32 bit 517 5 512 99 64 bit 261 5 256 98 conventional pci reads from host memory 2 32 bit 39 7 32 82 64 bit 23 7 16 70 8 32 bit 135 7 128 95 64 bit 71 7 64 90 32 32 bit 519 7 512 99 64 bit 263 7 256 97 pcix writes to host memory 2 32 bit 41 9 32 78 64 bit 25 9 16 64 8 32 bit 137 9 128 93 64 bit 73 9 64 88 32 32 bit 521 9 512 98 64 bit 265 9 256 97 pcix reads from host memory 2 32 bit 41 9 32 78 64 bit 25 9 16 64 8 32 bit 137 9 128 93 64 bit 73 9 64 88 32 32 bit 521 9 512 98 64 bit 265 9 256 97 table 6: bandwidth percentages.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 39 4.6.2 latency the following table provides some latency values measured in an ideal-model simulation environment. this data is provided for guidance, with no guarantee that it represents the exact behavior of a real-world system design. for these measurements: link a is 16 bits, 800 mhz; link b is 8 bits, 800 mhz; the host is connected to link a; no other traffic is present except the transactions described; latency is measured from the first clock in which the transaction is clocked into the ic until the first clock in which the transaction is clocked out of the ic. latency (ns) description 75-85 read response from link a to link b. 65-75 read response from link b to link a. 225-235 read request from conventional pci, 33 mhz, any width (32 or 64 bit), to link a. 300-310 read response from link a to conventional pci, 33 mhz, any width. 135-145 read request from conventional pci, 66 mhz, any width, to link a. 180-190 read response from link a to conventional pci, 66 mhz, any width. 180-190 read request from pci-x ? , 66 mhz, any width, to link a. 180-190 read response from link a to pci-x ? , 66 mhz, any width. 130-140 read request from pci-x ? , 100 mhz, any width, to link a. 145-155 read response from link a to pci-x ? , 100 mhz, any width. 110-120 read request from pci-x ? , 133 mhz, any width, to link a. 135-145 read response from link a to pci-x ? , 133 mhz, any width. table 7: some latencies.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 40 5 registers 5.1 register overview the ic includes several sets of registers accessed through a variety of address spaces. io address space refers to register addresses that are accessed through x86 io instructions such as in and out. pci configuration space is typically accessed by the host through io cycles to cf8h and cfch. there is also memory space and indexed address space in the ic. 5.1.1 configuration space the address space for the ic configuration registers is broken up into busses , devices , functions , and, offsets , as defined by the link specification. it is accessed by hypertransport? technology-defined type 0 configuration cycles. the device number is mapped into bits[15:11] of the configuration address. the function number is mapped into bits[10:8] of the configuration address. the offset is mapped to bits[7:2] of the configuration address. the following diagram shows the devices in configuration space as viewed by software. device a, above, is programmed to be the link base unitid and device b is the link base unitid plus 1. 5.1.2 register naming and description conventions configuration register locations are referenced with mnemonics that take the form of dev[a|b]:[7:0]x[ff:0], where the first set of brackets contain the device number, the second set of brackets contain the function num- ber, and the last set of brackets contain the offset. other register locations (e.g., memory mapped registers) are referenced with an assigned mnemonic that speci- fies the address space and offset. these mnemonics start with two or three characters that identify the space followed by characters that identify the offset within the space. register fields within register locations are also identified with a name or bit group in brackets following the register location mnemonic. figure 12: configuration space. primary bus pcix bridge devb:0xxx bridge header second device function 0 secondary bus external pcix bus devices pcix bridge deva:0xxx bridge header first device function 0 secondary bus external pcix bus devices ioapic deva:1xxx device header first device function 1 ioapic devb:1xxx device header second device function 1
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 41 the following are configuration spaces: the ic does not claim configuration-register accesses to unimplemented functions within its devices (they are forwarded to the other side of the tunnel). accesses to unimplemented register locations within implemented functions are claimed; such writes are ignored and reads always respond with all zeros. the following are memory mapped spaces: the following are register attributes found in the register descriptions. 5.2 pci-x ? bridge configuration registers these registers are located in pci configuration space, in the first device (device a) and second device (device b), function 0. see section 5.1.2 for a description of the register naming convention. device function mnemonic registers "a" 0 deva:0xxx pci-pci bridge a registers; link and pci-x ? capabilities block "a" 1 deva:1xxx ioapic for pci-x ? bridge a. "b" 0 devb:0xxx pci-pci bridge b registers; pci-x ? capabilities block "b" 1 devb:1xxx ioapic for pci-x ? bridge b. table 8: configuration spaces. base address register size (bytes) mnemonic registers dev[b,a]:1x10/48 4k ioaxx ioapic registers. base address register at offset 10h enabled by dev[b, a]:1x44[osvisbar]. dev[b,a]:0x10 4k shpc[b,a]: xx standard hot plug controller register set. access to these registers is enabled by deva:0x48[hpenb, hpena]. access to these registers is provided through both memory space and configuration space; to access through configuration space, dev[b, a]:0x90[select] specifies the dword offset and dev[b, a]:0x94 provides the dword data port. table 9: memory mapped address spaces. type description read or read-only capable of being read by software. read-only implies that the register cannot be written to by software. write capable of being written by software. set by hardware register bit is set high by hardware. write once after reset#, these registers may be written to once. after being written, they become read only until the next reset# assertion. the write-once control is byte based. so, for example, software may write each byte of a write-once dword as four individual transactions. as each byte is written, that byte becomes read only. write 1 to clear software must write a 1 to the bit in order to clear it. writing a 0 to these bits has no effect. write 1 only software can set the bit high by writing a 1 to it. however subsequent writes of 0 will have no effect. reset# must be asserted in order to clear the bit. table 10: register attributes.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 42 pci-x bridge vendor and device id register dev[b, a]:0x00 default: 7450 1022h attribute: read only. pci-x bridge status and command register dev[b, a]:0x04 default: 0230 0000h attribute: see below. bits description 31:16 pci bridge device id. 15:0 vendor id. bits description 31 dpe: detected parity error. read only. this bit is fixed in the low state. 30 sse: signaled system error. read; set by hardware; write 1 to clear. 1=a system error was signaled (both links were flooded with sync packets). this bit cannot be set unless dev[b, a]:0x04[serren] is high. note: this bit is cleared by pwrok reset but not by reset#. 29 rma: received master abort. read; set by hardware; write 1 to clear. 1=a request sent to the host bus received a master abort (an nxa error response). note: this bit is cleared by pwrok reset but not by reset#. 28 rta: received target abort. read; set by hardware; write 1 to clear. 1=a request sent to the host bus received a target abort (a non-nxa error response). note: this bit is cleared by pwrok reset but not by reset#. 27 sta: signaled target abort. read; set by hardware; write 1 to clear. 1=a target abort was signaled to the host (a non-nxa error response). note: this bit is cleared by pwrok reset but not by reset#. 26:21 read only. these bits are fixed in their default state. 20 capabilities pointer. read only. this bit is fixed in the high state. 19:9 reserved 8 serren: serr# enable. read-write. 1=dev[b, a]:0x04[sse] is enabled to be set high in response to detected system errors. 0=dev[b, a]:0x04[sse] cannot be set high and the ic does not flood the links with sync packets. 7 reserved. 6 persp: parity error response. read-write. this bit controls no hardware. it is provided for compatibility with the pci-pci bridge specification. 5 reserved. 4 mwien: memory write and invalidate enable. read-write. this bit does not control any internal hardware; it is provided for compatibility with the pci-pci bridge specification. 3 special cycle enable. read only. this bit is hardwired low. 2 masen: pci master enable. read-write. 1=enables secondary bus masters to initiate cycles to the host. 1 memen: memory enable. read-write. 1=enables access to the secondary bus memory space and to the shpc register space through the memory-space bar, dev[b, a]:0x10 (this bit does not affect access to shpc registers through configuration space, dev[b, a]:0x[94:90]). 0 ioen: io enable. read-write. 1=enables access to the secondary bus io space.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 43 pci-x bridge revision and class code register dev[b, a]:0x08 default: 0604 0?11h attribute: read only. pci-x bridge bist-header-latency-cache register dev[b, a]:0x0c default: 0081 ??00h attribute: see below. pci-x shpc base address register dev[b, a]:0x10 this register is reserved if deva:0x48[hpenb, hpena] is low. default: 0000 0000 0000 0004h attribute: see below. bits description 31:8 classcode. provides the bridge class code as defined in the pci specification. bits[3:1] of this register are zero. deva:0x08[8] is the same as deva:0x48[compat]. devb:0x08[8] is zero. 7:0 revision. bits description 31:24 bist. read only. these bits are fixed at their default values. 23:16 header. read only. these bits are fixed at their default values. 15:8 latency. read-write. these bits control no hardware. the default value after the deassertion of reset# is 00h when the bridge is in conventional pci mode and 40h when the bridge is in pci-x ? mode. 7:0 cache. read only. these bits are fixed at their default values. bits description 63:12 shpcbar: shpc base address register. read-write. these bits specify the memory address space of the shpc register set, shpc[b, a]:xx. note: bits[63:40] are required to be programmed low; setting any of these bits high results in undefined behavior. 11:0 hardwired. read only. these bits are all hardwired to their default state to indicate a 4k byte block of 64-bit, non-prefetchable memory space.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 44 pci-x bridge bus numbers and secondary latency register dev[b, a]:0x18 default: ??00 0000h attribute: see below. pci-x bridge memory base-limit registers dev[b, a]:0x[30:1c] these registers specify the io-space (dev[b, a]:0x1c and dev[b, a]:0x30), non-prefetchable memory-space (dev[b, a]:0x20), and prefetchable memory-space (dev[b, a]:0x24, dev[b, a]:0x28, and dev[b, a]:0x2c) address windows for transactions that are mapped from the 40-bit link address space to the secondary pci bus. the links support 25 bits of io space. pci-x supports 32 bits of io space. host accesses to the link-defined io region are mapped to the pci-x io window with the 7 msb always zero. pci-x io accesses in which any of the 7 msbs are other than zero are ignored. the pci-x io space window is defined as follows: pci-x io window = {7'h00, dev[b,a]:30[24:16], dev[b,a]:0x1c[15:12], 12'hfff} >= address >= {7'h00, dev[b,a]:30[8:0], dev[b,a]:0x1c[7:4], 12'h000}; the links and pci-x support 40 bits of memory space. the pci-x non-prefetchable memory space window is defined as follows: pci-x non-prefetchable memory window = {24'h00, deva:0xd8[15:8], dev[b,a]:0x20[31:20], 20'hf_ffff} >= address >= {24'h00, deva:0xd8[7:0], dev[b,a]:0x20[15:4], 20'h0_0000}; the links support 40 bits of memory space. pci-x supports 64 bits of prefetchable memory space. all link memory mapped io space may be within the pci-x prefetchable memory window. pci-x memory accesses in which any of bits[63:40] are other than zero are ignored. the pci-x prefetchable memory space window is defined as follows: pci-x prefetchable memory window = {24'h0, dev[b,a]:2c[7:0], dev[b,a]:0x24[31:20], 20'hf_ffff} >= address >= {24'h0, dev[b,a]:28[7:0], dev[b,a]:0x24[15:4], 20'h0_0000}; these windows may also be altered by dev[b, a]:0x3c[vgaen, isaen]. when the address (from either the host or from a secondary bus master) is inside one of the windows, then the transaction is assumed to be intended for a target that sits on the secondary bus. therefore, the following transactions are possible: ? host-initiated transactions inside the windows are routed to the secondary bus. ? secondary pci-initiated transactions inside the windows are not claimed by the ic. bits description 31:27 seclat[7:3]. read-write. secondary latency timer. the default value of seclat[7:0] after the deassertion of reset# is 00h when the bridge is in conventional pci mode and 40h when the bridge is in pci-x ? mode. 26:24 seclat[2:0]. read only, 000b. secondary latency timer. 23:16 subbus. read-write. subordinate bus number. 15:8 secbus. read-write. secondary bus number. 7:0 pribus. read-write. primary bus number.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 45 ? host initiated transactions outside the windows are passed through the tunnel or master aborted if the ic is at the end of a chain. ? secondary pci-initiated transactions outside the windows are claimed by the ic using medium decoding and passed to the host. so, for example, if iobase > iolim, then no host-initiated io-space transactions are forwarded to the sec- ondary bus and all secondary-pci-bus-initiated io-space (not configuration) transactions are forwarded to the host. if membase > memlim and pmembase > pmemlim, then no host-initiated memory-space trans- actions are forwarded to the secondary bus and all secondary-pci-bus-initiated memory-space transactions are forwarded to the host. the window may be affected by deva:0x48[compat] as well. dev[b, a]:0x1c . default: 0220 01f1h attribute: see below. dev[b, a]:0x20 . default: 0000 fff0h attribute: read-write. bits description 31 dpe: detected parity error. read; set by hardware; write 1 to clear. 1=the ic detected an address parity error as the target of a secondary bus cycle or a data parity error during a data phase of an upstream transaction. 30 rse: received system error. read; set by hardware; write 1 to clear. 1=the ic detected that either [b, a]_serr# or [b, a]_shpc_serr is asserted. in order to clear this bit, these signals must be deasserted. note: this bit is cleared by pwrok reset but not by reset#. 29 rma: received master abort. read; set by hardware; write 1 to clear. 1=the ic received a master abort as a master on the secondary bus. note: this bit is cleared by pwrok reset but not by reset#. 28 rta: received target abort. read; set by hardware; write 1 to clear. 1=the ic received a target abort as a master on the secondary pci bus. note: this bit is cleared by pwrok reset but not by reset#. 27 sta: signaled target abort. read; set by hardware; write 1 to clear. 1=the ic generated a target abort as a target on the secondary pci bus. note: this bit is cleared by pwrok reset but not by reset#. 26:25 device select timing. read only. these bits are hard wired to indicate medium decoding. 24 mdpe: master data parity error. read; set by hardware; write 1 to clear. 1=the ic detected a parity error during a data phase of a read or detected [b, a]_perr# asserted during a write as a master on the secondary bus and dev[b, a]:0x3c[peren] is set. 23 fbben: fast back to back enable. read only. this bit is fix in the low state to indicate that the ic does not support fast back to back transactions from different masters. 22:16 read only. these bits are fixed in their default state. 15:12 iolim. io limit address bits[15:12]. see dev[b, a]:0x[30:1c] above. 11:8 reserved. 7:4 iobase. io base address bits[15:12]. see dev[b, a]:0x[30:1c] above. 3:0 reserved. bits description 31:20 memlim. non-prefetchable memory limit address bits[31:20]. see dev[b, a]:0x[30:1c] above.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 46 dev[b, a]:0x24 . default: 0001 fff1h attribute: read-write. dev[b, a]:0x28 . default: 0000 0000h attribute: read-write. dev[b, a]:0x2c . default: 0000 0000h attribute: read-write. dev[b, a]:0x30 . default: 0000 ffffh attribute: read-write. pci-x bridge capabilities pointer register dev[b, a]:0x34 default: 0000 00a0h attribute: read only. pci-x bridge interrupt and bridge control register dev[b, a]:0x3c default: 0000 0?ffh attribute: see below. 19:16 reserved. 15:4 membase. non-prefetchable memory base address bits[31:20]. see dev[b, a]:0x[30:1c] above. 3:0 reserved. bits description 31:20 pmemlim. prefetchable memory limit address bits[31:20]. see dev[b, a]:0x[30:1c] above. 19:16 reserved. 15:4 pmembase. prefetchable memory base address bits[31:20]. see dev[b, a]:0x[30:1c] above. 3:0 reserved. bits description 31:0 pmembase. prefetchable memory base address bits[63:32]. see dev[b, a]:0x[30:1c] above. bits description 31:0 pmemlim. prefetchable memory limit address bits[63:32]. see dev[b, a]:0x[30:1c] above. bits description 31:16 iolim. io limit address bits[31:16]. see dev[b, a]:0x[30:1c] above. 15:0 iobase. io base address bits[31:16]. see dev[b, a]:0x[30:1c] above. bits description 31:8 reserved. 7:0 capabilities_ptr. specifies the offset to standard pci-x ? registers. bits description 31:28 reserved.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 47 27 dtse: discard timer sync flood enable. read-write. 1=if both dev[b, a]:0x04[serren] and dev[b, a]:0x3c[dts] are high, then dev[b, a]:0x04[sse] is set and the links are flooded with sync packets. 26 dts: discard timer status. read; set by hardware; write 1 to clear. 1=the 15-bit discard timer timed out. this bit is not capable of being set when the secondary bus is in pci-x ? mode. note: this bit is cleared by pwrok reset but not by reset#. 25:23 reserved. 22 sbrst: secondary bus reset. read-write. 1=[b, a]_preset# asserted; secondary pci bus placed into reset state. 0=[b, a]_preset# not asserted. note: the pci requirement for a delay between the rising edge of rst# and the first configuration access is not enforced by the ic with hardware; it is expected that this requirement be enforced through software. 21 marsp: master abort response. read-write. 1=the response to non-posted requests that come from the host bus or secondary bus that results in a master aborts will indicate a target abort to the initiating bus (through pci bus protocol or link protocol); posted requests that are master aborted result in assertion of dev[b, a]:0x04[sse]. 0=master aborts result in normal responses; read responses are sent with the appropriate amount of data, which are all 1s, and writes are ignored. 20 reserved. 19 vgaen: vga decoding enable. read-write. 1=route host-initiated commands targeting vga- compatible address ranges to the secondary bus. these include memory accesses from a0000h to bffffh (within the bottom megabyte of memory space only), io accesses in which address bits[9:0] range from 3b0h to 3bbh or 3c0h to 3dfh (address bits[15:10] are not decoded, regardless of dev[b, a]:0x3c[isaen]; also this only applies to the first 64k of io space; i.e., address bits[31:16] must be low). 0=the ic does not decode vga-compatible address ranges. 18 isaen: isa decoding enable. read-write. 1=the io address window specified by dev[b, a]:0x1c[15:0] and dev[b, a]:0x30 is limited to the first 256 bytes of each 1k byte block specified; this only applies to the first 64k bytes of io space. 0=the pci io window is the whole range specified by dev[b, a]:0x1c[15:0] and dev[b, a]:0x30. 17 serren: system error enable. read-write. if dev[b, a]:0x04[serren] and dev[b, a]:0x3c[serren] are both high and if [b, a]_serr# or [b, a]_shpc_serr is detected asserted (dev[b, a]:0x1c[rse] = 1), then the ic responds by flooding the outgoing link with sync packets and sets dev[b, a]:0x04[sse]. if either dev[b, a]:0x04[serren] or dev[b, a]:0x3c[serren] are low, then dev[b, a]:0x1c[rse] does not stop link operation or cause dev[b, a]:0x04[sse] to be set. 16 peren: parity error response enable. read-write. 1=enable parity error detection on secondary pci interface (see dev[b, a]:0x1c[mdpe]); [b, a]_perr# signal enabled to set status bit or be driven. 0=dev[b, a]:0x1c[mdpe] cannot be set; [b, a]_perr# signal is ignored and it is not driven by the ic. 15:8 interrupt_pin. read only. if deva:0x48[hpenb, hpena] is low, then dev[b, a]:0x3c[interrupt_pin] is 00h. if deva:0x48[hpenb, hpena] is high, then dev[b, a]:0x3c[interrupt_pin] is 01h. when hot plug mode is enabled, [b, a]_pirqa# can be asserted for hot plug events. 7:0 interrupt_line. read-write. these bits control no internal logic.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 48 pci-x miscellaneous register dev[b, a]:0x40 default: 001f 0001h. attribute: see below. bits description 31:28 pclkdel: [b, a]_pclk[4:0] delay. read-write. relative to [b, a]_pllclko, [b, a]_pclk[4:0] are delayed by pclkdel*tap_delay, where tap_delay is defined by deva:0x48[bdcv]. when a new value is written to this field, there may be a glitch on the output clocks. if [b, a]_pclk[4:0] are used as the reference clock to plls external to the ic, then changing this field may cause these plls to lose synchronization. for this reason, it is recommended that [b, a]_preset# be asserted (through dev[b, a]:0x3c[sbrst]) while this field is updated and that [b, a]_preset# be deasserted at least 1 millisecond after this field is updated. see section 4.3 for more information about [b, a]_pclk[4:0]. 27:24 pllodel: pllclko delay. read-write. relative to [b, a]_pclk[4:0], [b, a]_pllclko is delayed by pllodel*tap_delay, where tap_delay is defined by deva:0x48[bdcv]. when a new value is written to this field, the clock delay is shifted such that there is no glitch on the output signal. changing this field may cause the internal pll that generates [b, a]_pclk[4:0] to lose synchronization for a period of no more than 100 microseconds. for this reason, it is recommended that software alter this value by only one at a time. e.g., to change from 0 to 3, software should write a 1, then write a 2, then write a 3 to this field. see section 4.3 for more information about [b, a]_pllclko. 23:21 reserved. 20:16 pclken: pclk enable. read-write. each of these bits controls a [b, a]_pclk[4:0] signal. bit 16 controls pclk 0, bit 17 controls pclk1, and so forth. 1=the pclk signal is enabled to toggle. 0=the pclk signal is forced low. it is intended that this be used to disable pclk signals that correspond to unimplemented pci-x ? devices or slots. 15:13 reserved. 12:8 pfen[4:0]#: prefetch enables (active low). read-write. each of these bits apply to one [b, a]_req#/gnt# pair (dev[b, a]:0x40[pfen0#] applies to [b, a]_req0#/gnt0# and so forth). 0=prefetching is enabled for the specified external master in conventional pci mode. 1=prefetching is not enabled. when prefetching is not enabled, memory read requests from external masters are allowed to burst from the transaction starting address up to the 64-byte cacheline boundary, at which point the transaction is disconnected with data. if prefetching is enabled, while the burst is taking place, the next cacheline is read from the host such that the burst may be continued for multiple cachelines. this field is ignored when the bridge is in pci-x ? mode (dev[b, a]:0xa0[scf] is not zero). it is expected that these bits are normally left at 0. 7:5 reserved. 4 nzseqid: non-zero sequence id. read-write. 0=the seqid value is 0h in the upstream link requests that result from the bridges pci master memory read requests. 1=the seqid value is not zero in the upstream link requests that result from the bridges pci master memory read requests; if deva:0x40[nzseqid] is high, then a seqid of 1h is generated for these transactions from bridge a; if devb:0x40[nzseqid] is high, then a seqid of 2h is generated for these transactions from bridge b. this applies only to memory read requests from external masters. setting these bits high may reduce host memory efficiency and bandwidth. it is not expected that these bits will need to be set; the order in which requests are delivered to destinations does not matter in most cases. 3 must be low. read-write. this bit is required to be low at all times; setting it high results in undefined behavior.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 49 pci-x miscellaneous ii register dev[b, a]:0x44 default: 0000 0000h. attribute: read-write. 2 hpsss#: hot plug single-slot support (active low). read only. the default state of deva:0x40[hpsss#] is captured off of hpsic at the rising edge of pwrok. the default state of devb:0x40[hpsss#] is captured off of b_gnt2# at the rising edge of pwrok. 0=if the bridge is in hot plug mode (as specified by deva:0x48[hpenb or hpena]), then the bridge supports a single hot plug slot without external isolation switches. in this mode, external isolation switches between the ic and the slot are not required. see section 4.5.3 for details. 1=external isolation switches are required for all hot plug slots. this bit is required to be high if more than one external device is supported by the bridge. if hpsss# is low while the deva:0x48[hpenb, hpena] bit corresponding to the same bridge is low, then undefined behavior results. 1 cpci66: conventional pci mode frequency. read only. dev[b, a]:0xa0[scf]=0h, then the bridge is in conventional pci mode and this bit is valid; otherwise its state is unknown. 0=[b, a]_pclk[4:0] toggle at 33 mhz. 1=[b, a]_pclk[4:0] toggle at 66 mhz. the default state for this field is determined by strapping options described in section 4.2. 0 nioamode: non-ioapic mode. read-write. this is used to enable [b, a]_pirq[d, c, b, a]# to the nioairq[d, c, b, a]# pins. 0=the state of the pirq[d:a]# pin is passed to the nioairq[d:a]# pin as if the pirq[d:a]# pin were always high. 1=the state of the pirq[d:a]# pin from the bridge is anded with the state from the other bridge and passed to the nioairq[d:a]# pin. this is shown in the following equations: nioairqa# = ~( deva:0x40[nioamode] & ~a_pirqa# & rdra0[im] | devb:0x40[nioamode] & ~b_pirqa# & rdrb0[im] ); nioairqb# = ~( deva:0x40[nioamode] & ~a_pirqb# & rdra1[im] | devb:0x40[nioamode] & ~b_pirqb# & rdrb1[im] ); and similarly for nioairq[c and d]#. were rdr[b, a][3:0][im] is the interrupt mask field of the redirection register (see section 5.4); [b, a] = the bridge letter; [3:0] = the redirection register index. note that the nioairq[d:a]# pins are open drain outputs. so a high on the pirq input is translated to the high-inpedence state on the nioairq output. see section 4.5.2 for more details about interrupt routing. it is expected that this bit is normally left high by system bios. bits description 31:1 rw. read-write. these bits control no hardware. these bits are reserved and should be left in the default state. 0 nmien: nmi on error enable. read-write. 1=assertions of the [b, a]_perr# and [b, a]_serr# signals (regardless of the source of the assertion) result in nmi interrupts; see section 4.5.2.1.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 50 pins latched at boot register deva:0x48 the default value for bits in this register is latched at the rising edge of pwrok. default: 0000 000?h. attribute: see below. prefetch control register dev[b, a]:0x4c this register specifies the prefetching policy when a bridge is in conventional pci mode. this register is ignored when in pci-x mode. it includes three sets of initial prefetch registers (ipf_x) and three corresponding sets of continuous prefetch enable registers (cpfen_x): one for memory read multiple requests (x=mrm); one for memory read line requests (x=mrl); and one for memory read requests (x=mr). when a pci master, for which prefetching is enabled through dev[b, a]:0x40[pfen#], initiates a host read with a command code of mrm, mrl, or mr, then the ic sends link read requests as follows: (1) an initial up-to-one cacheline request from the initial address to the end of the cacheline and (2) additional cachelines as specified by the ipf_x field that corresponds to the command code issued by the pci master. when each cacheline of data starts to be transferred to the master over the pci bus, an additional cacheline of data may be requested, as specified by the appropriate cpfen_x bit. an unrequested prefetch , as specified in some of the fields of this register, is a speculative link request--or prefetch--generated by the ic for a cacheline of data beyond the cach- eline address generated by the conventional pci master; a requested prefetch is up-to-one cacheline of memory read data at an address generated by the conventional pci master. see section 4.6.1 for information about how prefetching is related to performance. default: 0000 2c00h. attribute: read-write. bits description 31:12 reserved. 11:8 bdcv: buffer delay calculation value. read only. this provides the approximate buffer delay calculation value used to determine the delay value of each tap in dev[b, a]:0x40[pllodel and pclkdel] as follows: tap_delay ~= 1250/bdcv picoseconds. expected values for bdcv are from 5h to fh. 7:4 reserved. 3 hpenb: bridge b hot plug enable. read only. this bit captures the state of hpsil# at the rising edge of pwrok. 0=hot plug mode is not enabled on bridge b. 1=hot plug mode is enabled on bridge b. see section 4.5.3 for details. if this bit is low while devb:0x40[hpsss#] is low, then undefined behavior results. 2 hpena: bridge a hot plug enable. read only. this bit captures the state of hpsod at the rising edge of pwrok. 0=hot plug mode is not enabled on bridge a. 1=hot plug mode is enabled on bridge a. see section 4.5.3 for details. if this bit is low while deva:0x40[hpsss#] is low, then undefined behavior results. 1 reserved. 0 compat: compatibility bus. read-write. 1=the ic routes all host initiated accesses in which the link-defined compat bit is set to the secondary bus. the default state of this bit is latched off of a_compat at the trailing edge of pwrok reset. bits description 31:14 reserved.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 51 13 cpfen_mrm. continuous prefetch enable for memory read multiple request. when a master initiates a burst read to the host with a memory read multiple command code, this specifies if continu- ous prefetching is enabled. 1 = one new request for a cacheline of prefetch data is sent to the host by the ic when data from an earlier cacheline starts to be transferred to the requesting master over the pci bus. 0 = there are no new requests for prefetch data after the initial batch specified by ipf_mrm. 12:10 ipf_mrm: initial prefetch for memory read multiple request. this specifies the number of addi- tional cacheline prefetches (after the initial prefetch of up to one cacheline) when a pci master ini- tiates a burst read to the host with a memory read multiple command code. if prefetching is disabled in dev[b, a]:0x40[pfen#], then the value of this register is ignored. 0=no additional prefetches; 1=1 additional prefetch; 2=2 additional prefetches, and so forth. 9 cpfen_mrl. continuous prefetch enable for memory read line request. see cpfen_mrm. 8:6 ipf_mrl: initial prefetch for memory read line request. see ipf_mrm. 5 cpfen_mr. continuous prefetch enable for memory read request. see cpfen_mrm. 4:2 ipf_mr: initial prefetch for memory read request. see ipf_mrm. 1 dpdm: discard unrequested prefetch data upon master request. 1=no further prefetching occurs and all unrequested prefetches are discarded when another master requests the pci bus; also, unre- quested prefetches are discarded if the discard timer reaches 16 pclks (requested prefetches are dis- carded if the discard timer reaches 32k pclks). 0=requests from other masters do not affect prefetching; requested and unrequested prefetches are discarded if the discard timer reaches 32k pclks. this bit is typically programmed low by system bios. 0 dpdh: discard unrequested prefetch data upon host request. 1=if the ic receives a host request to the pci bus, then: (1)if there is not an outstanding requested prefetch for a given previously-established pci read request, then all of the unrequested prefetches associated with that pci read request are dis- carded; or (2)if there is an outstanding requested prefetch for a given previously-established pci read request, then the data for that requested prefetch, along with the data for subsequent unrequested prefetches, is allowed to burst onto the pci bus until the burst is disconnected (either by the pci master or by the ic because it does not possess the data necessary to continue the burst); when the burst is disconnected, any remaining unrequested prefetches associated with the pci read request are discarded. (3)if there is a burst in progress on the pci bus, the ic disconnects the burst at the next convenient cacheline boundary and discards any outstanding unrequested prefetches associated with the transaction. 0=host requests do not affect prefetching. programming of this bit may vary based on platform requirements. dpdh is typically programmed high by system bios to protect against stale prefetch-data scenarios, as described in the pci specifi- cation, revision 2.3, section 3.10, point 6; scenarios similar to this have been observed, albeit rarely. however, if the secondary pci bus includes a device that is accessed frequently as a target, then set- ting this bit may result in reduced memory read bandwidth. in such cases, it may be preferable to pro- gram this bit low.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 52 pci-x phy compensation control registers deva:0x[54, 50] the pci-x phy circuitry includes automatic compensation that is used to adjust the drive strength of the pci- x and other io cells, including all output signals of the ic that are on the vdd33 power plane. the compensa- tion circuits calculate the drive strength for the rising edge and falling edge of the outputs. these registers pro- vide visibility into the calculated output of the compensation circuits, the ability to override the calculated value with software-controlled values, and the ability to offset the calculated values with a fixed difference. the overrides and difference values may be different between bridges a and b. these registers specify the compensation parameters as follows: ? deva:0x50: output rising edge (p) drive strength compensation; associated with the p_cal pin. ? deva:0x54: output falling edge (n) drive strength compensation; associated with the p_cal# pin. higher values in these registers represent higher drive strength; the values range from 0h to fh (16 steps). default: 0000 0000. attribute: see below. bits description 31 must be low. read-write. this bit is required to be low at all times; setting it high results in undefined behavior. 30:20 reserved. 19:16 calccomp: calculated compensation value. read only. this provides the calculated value from the auto compensation circuitry. the default value of this field is not predictable. deva:0x50[calccomp] is affected by the value of the resistor connected to p_cal and deva:0x54[calccomp] is affected by the value of the resistor connected to p_cal#. in both cases, larger the values of resistors (measured in ohms) result in smaller calccomp values. 15 reserved. 14:13 bctl: bridge b phy control value. read-write. these two bits combine to specify the phy compensation value that is applied to bridge b outputs as follows: bctl description 00b apply calccomp directly as the compensation value. 01b apply bdata directly as the compensation value. 10b apply the sum of calccomp and bdata as the compensation value. if the sum exceeds fh, then fh is applied. 11b apply the difference of calccomp minus bdata as the compensation value. if the difference is less than 0h, then 0h is applied. 12 reserved. 11:8 bdata: bridge b data value. read-write. this value is appled to the bridge b phy compensation as described in bctl. 7 reserved.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 53 shpc capabilities register dev[b, a]:0x90 this register is reserved if deva:0x48[hpenb, hpena] is low. default: 0000 980ch attribute: see below. shpc data register dev[b, a]:0x94 this register is reserved if deva:0x48[hpenb, hpena] is low. default: 0000 0000h attribute: read-write. 6:5 actl: bridge a phy control value. read-write. these two bits combine to specify the phy compensation value that is applied to bridge a outputs as follows: actl description 00b apply calccomp directly as the compensation value. 01b apply adata directly as the compensation value. 10b apply the sum of calccomp and adata as the compensation value. if the sum exceeds fh, then fh is applied. 11b apply the difference of calccomp minus adata as the compensation value. if the difference is less than 0h, then 0h is applied. 4 reserved 3:0 adata: bridge a data value. read-write. this value is appled to the bridge a phy compensation as described in actl. bits description 31 cip: controller interrupt pending. read only. 1=one or more bits in shpc[b, a]:18 is set. 0=all bits in shpc[b, a]:18 are cleared. 30 cserrp: controller system error pending. read only. 1=one or more bits in shpc[b, a]:1c is set. 0=all bits in shpc[b, a]:1c are cleared. 29:24 reserved. 23:16 select: dword select. read-write. specifies the dword from the shpc[b, a]:xx register set that is accessible through dev[b, a]:0x94. 00h selects shpc[b, a]:00; 01h selects shpc[b, a]:04; and so on. 15:8 next capability pointer. read only. points to the next capability block. 7:0 capabilities id. read only. specifies the capabilities id for shpc. bits description 31:0 data: shpc data port. accesses to this port access the register of the shpc[b, a]:xx register set that is indexed by dev[b, a]:0x90[select].
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 54 power management capabilities register dev[b, a]:0x98 this register is reserved if deva:0x48[hpenb, hpena] is low. default: 480a ??01h attribute: read only. power management status and control register dev[b, a]:0x9c this register is reserved if deva:0x48[hpenb, hpena] is low. default: 0000 0000h attribute: see below bits description 31:27 pmes: pme support. indicates pme# support in device state d0 (system state s0) and device state d3 hot (system state s1). 26 d2s: d2 support. indicates that d2 device power state is not supported. 25 d1s: d1 support. indicates that d1 device power state is not supported. 24:22 auxcr: auxiliary current requirements. indicates that there is no requirement for auxiliary current since the d3 cold device power state is not supported. 21 dsi: device specific initialization. indicates that there is no special initialization requirement. 20 reserved. 19 pmeclk: pme clock. indicates that the pci clock is required for pme# generation. 18:16 version. specifies that the pci function complies with revision 1.1 of the pci power management interface specification . 15:8 next capability pointer. read only. points to the next capability block. deva:0x98[15:8]=c0h. devb:0x98[15:8]=00h. 7:0 capabilities id. specifies the capabilities id for pci power managament. bits description 31:24 reserved. 23 bpcc_en: bus power/clock control enable. read only. indicates that the bus power/clock control policies defined in section 4.7.1 of the pci bus power management interface specification rev. 1.1 have been disabled. 22:16 reserved. 15 pme_sts: pme# status. read; set by hardware; write 1 to clear. set when [b, a]_pme# is asserted as a result of an shpc pme event (see shpc[b, a]:20). 14:9 reserved. 8 pme_en: pme enable. read-write. 1=enables [b, a]_pme# assertion if dev[b, a]:0x9c[pme_sts] is set. 7:2 reserved. 1:0 pwrs: power state. read-write. indicates the current power state of the function. 00b = d0. 11b = d3 hot. if software attempts to write unsupported state to this field (01b = d1 or 10b = d2), the write operation completes normally on the bus; however, the data is discarded and no state change occurs.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 55 pci-x secondary status register dev[b, a]:0xa0 default: 0??3 b807h (bits[21:20] reset to low; see below for bits[24:22]).attribute: see below. pci-x bridge status register dev[b, a]:0xa4 default: 0003 0000h attribute: see below. bits description 31:25 reserved. 24:22 scf: secondary clock frequency. read only. this specifies the frequency of the secondary bus the last time [b, a]_preset# was asserted. 0h=conventional pci mode; 1h=66 mhz pci-x ? mode; 2h=100 mhz pci-x ? mode; 3h=133 mhz pci-x ? mode; 4h-7h are reserved. the default state for this field is determined by strapping options described in section 4.2. 21 srd: split request delayed. read only; hardwired low. the ic automatically limits the number of upstream link read requests to the number of downstream buffers available; so there is no reason to limit the number of adqs in read requests accepted by the ic. 20 sco: split completion overrun. read only; hardwired low. the ic automatically limits the number of downstream pci-x ? read requests to the number of upstream response buffers available; so there is no reason to terminate a split completion for this reason. 19 usc: unexpected split completion. read; set by hardware; write 1 to clear. 1=an unexpected split completion with a requester id equal to the bridges secondary bus number, device number 00h, and function number 0 was received on the secondary interface. 18 scd: split completion discarded. read; set by hardware; write 1 to clear. 1=the bridge discarded a split completion moving toward the secondary bus because the requester would not accept it. 17 133 mhz capable. read only. this bit is hardwired high to indicate support for 133 mhz. 16 64-bit device. read only. this bit is hardwired high to indicate a 64-bit secondary bus. 15:8 next capability pointer. read only. points to the next capability block. 7:0 capabilities id. read only. specifies the capabilities id for pci-x ? configuration space. bits description 31:22 reserved. 21 srd: split request delayed. read only; hardwired low. the ic automatically limits the number of downstream pci-x ? read requests to the number of upstream buffers available; so there is no reason to limit the number of adqs in read requests accepted by the ic. 20 split completion overrun. read only. this bit is hardwired low. 19 unexpected split completion. read only. this bit is hardwired low. 18 split completion discarded. read only. this bit is hardwired low. 17 133 mhz capable. this bit is set high arbitrarily. it has no meaning since the primary bus is not pci- x ? . 16 64-bit device. read only. this bit is set high arbitrarily. it has no meaning since the primary bus is not pci-x ? . 15:8 bus number. read only. these bits reflect the state of dev[b, a]:0x18[pribus].
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 56 pci-x upstream split transaction register dev[b, a]:0xa8 default: ffff 000eh attribute: see below. pci-x downstream split transaction register dev[b, a]:0xac default: ffff 0002h attribute: see below. interrupt discovery configuration registers dev[b, a]:0x[bc, b8] these two locations duplicate access to the ioapic register space defined in section 5.4. dev[b, a]:0xb8[index] provides the index and dev[b, a]:0xbc provides the data port. the definition of the indexed registers is as described in section 5.4. some fields of the idrdr register are identical to rdr fields (im, pol, tm, dm, dest, irr); these represent duplicate access to the same physical registers (not duplicate registers). other idrdr fields (intrinfo, passpw) represent new functionality. see section 4.5.2 for more information about interrupts. 7:3 device number. read only. for deva, these bits reflect the state of deva:0xc0[buid]. fore devb, these bits reflect the state of deva:0xc0[buid] plus 1. 2:0 function number. read only. this is 0h to reflect the value of this function. bits description 31:16 ustcl: upstream split transaction commitment limit. read-write. this register controls no hardware. the ic automatically limits the number of upstream link read requests to the number of downstream buffers available; so there is no reason to limit the number of adqs in read requests accepted by the ic. this field is required to be greater than or equal to dev[b, a]:0xa8[ustc]. a value of ffffh specifies that there is no limit. it is expected that this register will be left at its default value by software. 15:0 ustc: upstream split transaction capacity. read only. this field specifies the number of downstream response adqs that can be stored for completion on the secondary bus. bits description 31:16 dstcl: downstream split transaction commitment limit. read-write. this register controls no hardware. the ic automatically limits the number of downstream pci-x ? read requests to the number of upstream buffers available; so there is no reason to limit the number of adqs in read requests gen- erated by the ic. this field is required to be greater than or equal to dev[b, a]:0xac[dstc]. a value of ffffh specifies that there is no limit. it is expected that this register will be left at its default value by software. 15:0 dstc: downstream split transaction capacity. read only. this field specifies the number of upstream response adqs that can be stored for completion to the link.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 57 dev[b, a]:0xb8. default: 8000 ??08h attribute: see below. idrdr. default: 0000 0000 f800 0001h attribute: see below. bits description 31:24 capability type. read only. this field is hardwired to indicate the link-defined interrupt discovery and configuration block. 23:16 index. read-write. specifies the register accessed through the dev[b, a]:0xbc dataport. this is the same as ioa00 described in section 5.4. 15:8 next capability pointer. read only. points to the next capability block. the value of this register varies as follows: ? if deva:0x48[hpena]=0 then deva:0xb8[18:5]=c0h (ht capability block). ? if deva:0x48[hpena]=1 then deva:0xb8[18:5]=90h (hot plug capability block). ? if deva:0x48[hpenb]=0 then devb:0xb8[18:5]=00h (last capability block). ? if deva:0x48[hpenb]=1 then devb:0xb8[18:5]=90h (hot plug capability block). 7:0 capabilities id. read only. specifies the capabilities id for link configuration space. bits description 63 irr. read; set by hardware; cleared by hardware or write 1 to clear. this provides duplicate access to rdr[irr] described in section 5.4. however, writing a 1 to this bit clears this register; this is not the case with rdr[irr]. 62 passpw. read-write. the state of this bit is reflected in the passpw bit of the link interrupt request packet. it is expected to be programmed low in all cases. 61:56 reserved. 55:24 intrinfo[55:24]. read-write. intrinfo[55:24] in the link interrupt request packet. 23:16 iv. read-write. intrinfo[23:16] in the link interrupt request packet. this provides duplicate access to rdr[iv] described in section 5.4. 15:8 dest. read-write. intrinfo[15:8] in the link interrupt request packet. this provides duplicate access to rdr[dest] described in section 5.4. 7 intrinfo[7]. read-write. intrinfo[7] in the link interrupt request packet. 6 dm. read-write. intrinfo[6] in the link interrupt request packet. this provides duplicate access to rdr[dm] described in section 5.4. 5 tm. read-write. intrinfo[5] in the link interrupt request packet. this provides duplicate access to rdr[tm] described in section 5.4. 4:2 mt. read-write. intrinfo[4:2] in the link interrupt request packet. accesses to rdr[mt] described in section 5.4. result in translated accesses to this field; see rdr[mt] for details. 1 pol. read-write. this provides duplicate access to rdr[pol] described in section 5.4. 0 im. read-write. this provides duplicate access to rdr[im] described in section 5.4.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 58 link command register deva:0xc0 default: 0040 0008h attribute: see below. link configuration and control register deva:0xc4 and deva:0xc8 deva:0xc4 applies side a of the tunnel and deva:0xc8 applies to side b of the tunnel. the default value for bit[5] may vary (see the definition). default: ??11 0020h for deva:0xc4 and ??00 0020h for deva:0xc8.attribute: see below. bits description 31:29 slave/primary interface type. read only. 28 doui: drop on uninitialized link. read-write. this specifies the behavior of transactions that are sent to uninitialized links. 0=transactions that are received by the ic and forwarded to a side of the tunnel, when deva:0x[c4/c8][initcplt and endoch] for that side of the tunnel are both low, remain in buffers awaiting transmission indefinitely (waiting for initcplt to be set high). 1=trans- actions that are received by the ic and forwarded to a side of the tunnel, when deva:0x[c4/c8][initcplt and endoch] for that side of the tunnel are both low, behave as if endoch were high. note: this bit is cleared by pwrok reset but not by reset#. 27 defdir: default direction. read-write. 0=send secondary pci bus master requests to the master link host as specified by deva:0xc0[mashst]. 1=send secondary pci bus master requests to the opposite side of the tunnel. 26 mashst: master host. read; set and cleared by hardware. this bit indicates which link is the path to the master (or only) host bridge on the hypertransport technology chain. 1=the hardware set this bit as a result of a write command from the b side of the tunnel to any of the bytes of deva:0xc0[31:16]. 0=the hardware cleared this bit as a result of a write command from the a side of the tunnel to any of the bytes of deva:0xc0[31:16]. this bit, along with defdir, is used to determine the side of the tunnel to which secondary pci bus master requests are sent. 25:21 unitid count. read only. specifies the number of unitids used by the ic (two). 20:16 buid: base unitid. read-write. this specifies the link-protocol base unitid. the ic's logic uses this value to determine the unitids for link request and response packets. when a new value is written to this field, the response includes a unitid that is based on the new value in this register. 15:8 reserved. 7:0 capabilities id. read only. specifies the capabilities id for link configuration space. bits description 31 reserved. 30:28 lwo: link width out. read-write. specifies the operating width of the outgoing link. legal values are 001b (16 bits; deva:0xc4 only), 000b (8 bits), 101b (4 bits), 100b (2 bits), and 111b (not connected). note: this field is cleared by pwrok reset but not by reset#; the default value of this field depends on the widths of the links of the connecting device, per the link specification. note: after this field is updated, the link width does not change until either reset# is asserted or a link disconnect sequence occurs through or ldtstop#. 27 reserved.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 59 26:24 lwi: link width in. read-write. specifies the operating width of the incoming link. legal values are 001b (16 bits; deva:0xc4 only), 000b (8 bits), 101b (4 bits), 100b (2 bits), and 111b (not connected). note: this field is cleared by pwrok reset but not by reset#; the default value of this field depends on the widths of the links of the connecting device, per the link specification. note: after this field is updated, the link width does not change until either reset# is asserted or a link disconnect sequence occurs through an ldtstop# assertion. 23 reserved. 22:20 max link width out. read only. this specifies the width of the outgoing link to be 16 bits wide for side a and 8 bits wide for side b. 19 reserved. 18:16 max link width in. read only. this specifies the width of the incoming link to be 16 bits wide for side a and 8 bits wide for side b. 15 reserved. 14 extctl: extended control time during initialization. read-write. this specifies the time in which lt[b, a]ctl is held asserted during the initialization sequence that follows an ldtstop# deassertion, after lr[b, a]ctl is detected asserted. 0=at least 16 bit times. 1=about 50 microseconds. note: this bit is cleared by pwrok reset but not by reset#. 13 ldt3sen: link three-state enable. read-write. 1=during the ldtstop# disconnect sequence, the link transmitter signals are placed into the high impedance state and the receivers are prepared for the high impedance mode. for the receivers, this includes cutting power to the receiver differential amplifiers and ensuring that there are no resultant high-current paths in the circuits. 0=during the ldtstop# disconnect sequence, the link transmitter signals are driven, but in an undefined state, and the link receiver signals are assumed to be driven. note: this bit is cleared by pwrok reset but not by reset#. amd recommends that this bit be set high in single-processor systems and be low in multi-processor systems. 12:10 reserved. 9:8 crcerr: crc error. read; set by hardware; write 1 to clear. bit[9] applies to the upper byte of the link (deva:0xc4 only) and bit[8] applies to the lower byte. 1=the hardware detected a crc error on the incoming link. note: this bit is cleared by pwrok reset but not by reset#. 7 txoff: transmitter off. read; write 1 only. 1=no output signals on the link toggle; the input link receivers are disabled and the pins may float. 6 endoch: end of chain. read; write 1 only or set by hardware. 1=the link is not part of the logical hypertransport technology chain; packets which are issued or forwarded to this link are either dropped or result in an nxa error response, as appropriate; packets received from this link are ignored and crc is not checked; if the transmitter is still enabled (txoff), then it drives only nop packets with good crc. endoch may be set by writing a 1 to it or it may be set by hardware if the link is determined to be disconnected at the rising edge of reset#. 5 initcplt: initialization complete. read only. this bit is set by hardware when low-level link initialization has successfully completed. if there is no device on the other end of the link, or if the device on the other side of the link is unable to properly perform link initialization, then the bit is not set. this bit is cleared when reset# is asserted or after the link disconnect sequence completes after the assertion of ldtstop#. 4 lkfail: link failure. read; set by hardware; write 1 to clear. this bit is set high by the hardware when a crc error is detected on the link (if enabled by crcfen) or if the link is not used in the system. note: this bit is cleared by pwrok reset, not by reset#.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 60 link frequency capability 0 register deva:0xcc default: 0035 0022h. attribute: see below. link frequency capability 1 register deva:0xd0 default: 0035 0002h. attribute: see below. 3 crcerrcmd: crc error command. read-write. 1=the link transmission logic generates erroneous crc values. 0=transmitted crc values match the values calculated per the link specification. this bit is intended to be used to check the crc failure detection logic of the device on the other side of the link. 2 reserved. 1 crcfen: crc flood enable. read-write. 1=crc errors (in link a for deva:0xc4[crcfen]; in link b for deva:0xc8[crcfen]) result in sync packets to both outgoing links and the lkfail bit is set. 0=crc errors do not result in sync packets or setting the lkfail bit. 0 reserved. bits description 31:16 freqcapa: link a frequency capability. read only. these bits indicate that a side of the tunnel supports 200, 400, 600, and 800 mhz link frequencies. 15:12 reserved. 11:8 freqa: link a frequency. read-write. specifies the link side a frequency. legal values are 0h (200 mhz), 2h (400 mhz), 4h (600 mhz), and 5h (800 mhz). note: this bit is cleared by pwrok reset, not by reset#. note: after this field is updated, the link frequency does not change until either reset# is asserted or a link disconnect sequence occurs through ldtstop#. 7:0 revision. read only. the ic is designed to version 1.02 of the link specification. bits description 31:16 freqcapb: link b frequency capability. read only. these bits indicate that that b side of the tunnel supports 200, 400, 600, and 800 mhz link frequencies. 15:12 reserved. 11:8 freqb: link b frequency. read-write. specifies the link side b frequency. legal values are 0h (200 mhz), and 2h (400 mhz), 4h (600 mhz), and 5h (800 mhz). note: this bit is cleared by pwrok reset, not by reset#. note: after this field is updated, the link frequency does not change until either reset# is asserted or a link disconnect sequence occurs through ldtstop#. 7:0 link device feature capability indicator. read only. these bits are set to indicate that the ic supports ldtstop#.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 61 link enumeration scratchpad register deva:0xd4 default: 0000 0000h. attribute: see below. link non-prefetchable memory space extension register deva:0xd8 default: 0000 0000h. attribute: read-write. link phy compensation control registers deva:0x[e8, e4, e0] the link phy circuitry includes automatic compensation that is used to adjust the electrical characteristics for the link transmitters and receivers on both sides of the tunnel. there is one compensation circuit for the receiv- ers and one for each polarity of the transmitters. these registers provide visibility into the calculated output of the compensation circuits, the ability to override the calculated value with software-controlled values, and the ability to offset the calculated values with a fixed difference. the overrides and difference values may be dif- ferent between sides a and b of the tunnel. these registers specify the compensation parameters as follows: ? deva:0xe0: transmitter rising edge (p) drive strength compensation. ? deva:0xe4: transmitter falling edge (n) drive strength compensation. ? deva:0xe8: receiver impedance compensation. for deva:0x[e4, e0], higher values represent higher drive strength; the values range from 01h to 13h (19 steps). for deva:0xe8, higher values represent lower impedance; the values range from 00h to 1fh (32 steps). note: the default state of these registers is set by pwrok reset; assertion of reset# does not alter any of the fields. default: see below. attribute: see below. bits description 31:16 reserved. 15:0 esp: enumeration scratchpad. read-write. this field controls no hardware within the ic. note: this bit is cleared by pwrok reset, not by reset#. bits description 31:16 reserved. 15:8 npuml: non-prefetchable upper memory limit. this field provides bits[39:32] of the non- prefetchable memory space address limit specified by dev[b, a]:0x20[memlim]. see dev[b,a]:0x1c for details. 7:0 npumb: non-prefetchable upper memory base. this field provides bits[39:32] of the non- prefetchable memory space address base specified by dev[b, a]:0x20[membase]. see dev[b,a]:0x1c for details. bits description 31 must be low. read-write. this bit is required to be low at all times; setting it high results in undefined behavior. 30:21 reserved. 20:16 calccomp: calculated compensation value. read only. this provides the calculated value from the auto compensation circuitry. the default value of this field is not predictable.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 62 15 reserved. 14:13 bctl: link side b phy control value. read-write. these two bits combine to specify the phy compensation value that is applied to side b of the tunnel as follows: bctl description 00b apply calccomp directly as the compensation value. 01b apply bdata directly as the compensation value. 10b apply the sum of calccomp and bdata as the compensation value. in deva:0x[e4, e0], if the sum exceeds 13h, then 13h is applied. in deva:0x[e8], if the sum exceeds 1fh, then 1fh is applied. 11b apply the difference of calccomp minus bdata as the compensation value. if the difference is less than 01h, then 01h is applied. the default value of this field (from pwrok reset) is controlled by the cmpovr signal. if cmpovr = 0, the default is 00b. if cmpovr = 1, the default is 01b. 12:8 bdata: link side b data value. read-write. this value is appled to the side b of the tunnel phy compensation as described in bctl. the default for deva:0x[e4, e0] is 08h. the default for deva:0xe8 is 0fh. 7 reserved. 6:5 actl: link side a phy control value. read-write. these two bits combine to specify the phy compensation value that is applied to side a of the tunnel as follows: actl description 00b apply calccomp directly as the compensation value. 01b apply adata directly as the compensation value. 10b apply the sum of calccomp and adata as the compensation value. in deva:0x[e4, e0], if the sum exceeds 13h, then 13h is applied. in deva:0x[e8], if the sum exceeds 1fh, then 1fh is applied. 11b apply the difference of calccomp minus adata as the compensation value. if the difference is less than 01h, then 01h is applied. the default value of this field (from pwrok reset) is controlled by the cmpovr signal. if cmpovr = 0, the default is 00b. if cmpovr = 1, the default is 01b. 4:0 adata: link side a data value. read-write. this value is appled to the side a of the tunnel phy compensation as described in actl. the default for deva:0x[e4, e0] is 08h. the default for deva:0xe8 is 0fh.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 63 clock control register deva:0xf0 see section 4.3.3 for details on clock gating. amd system recommendations for system management action field (smaf) codes are: 0=acpi c2; 1=acpi c3; 2=fid/vid change; 3=acpi s1; 4=acpi s3; 5=throt- tling; 6=acpi s4/s5. amd recommends setting this register to 0004_0008h (to gate clocks during s1). default: 0000 0000h. attribute: read-write. 5.3 pci-x ioapic configuration registers these registers are located in pci configuration space, in the first device (device a) and second device (device b), function 1. see section 5.1.2 for a description of the register naming convention. ioapic vendor and device id register dev[b, a]:1x00 default: 7451 1022h attribute: read only. ioapic status and command register dev[b, a]:1x04 default: 0200 0000h attribute: see below. bits description 31:19 reserved. 18 cgen: clock gate enable. 1=internal clock gating, as specified by bits[7:0] of this register, is enabled. 17 must be low. this bit is required to be low at all times; setting it high results in undefined behavior. 16 must be low. this bit is required to be low at all times; setting it high results in undefined behavior. 15:8 reserved. 7:0 icgsmaf: internal clock gating system management action fields. each of the bits of this field correspond to smaf values that are captured in stop grant cycles from the host. for each bit, 1=when ldtstop# is asserted prior to a stop grant cycle in which the smaf field matches the icgsmaf bit that is asserted, then the ic power is reduced through gating of internal clocks. 0=no power reduction while ldtstop# is asserted. for example, if clock gating is required for smaf values of 3 and 5, then icgsmaf[3, 5] must be high. see section 4.3.3 for details. bits description 31:16 ioapic device id. 15:0 vendor id. bits description 31:3 read only. these bits are fixed in their default state. 2 masen: pci master enable. read-write. 1=enables ioapic to initiate interrupt requests to the host. note: if dev[b, a]:1x44[osvisbar]=0, then the state of this bit is ignored. note: dev[b, a]:1x44[ioaen] must be high to enable interrupt requests, regardless of the state of this bit.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 64 ioapic revision and class code register dev[b, a]:1x08 default: 0800 1001h attribute: read only. ioapic device bist-header-latency-cache register dev[b, a]:1x0c default: 0000 0000h attribute: read only. ioapic base address register dev[b, a]:1x10 and dev[b, a]:1x48 offsets 10h and 48h provide access to the same 8-byte register. offset 48h is always accessible. however, off- set 10h can be disabled from read and write access through dev[b, a]:1x44[osvisbar]. default: 0000 0000 0000 0004h attribute: see below. ioapic device subsystem id and subsystem vendor id register dev[b, a]:1x2c default: 0000 0000h attribute: read; write once. 1 memen: memory enable. read-write. 1=enables access to the memory space specified by deva:1x10. note: if dev[b, a]:1x44[osvisbar]=0, then the state of this bit is ignored. note: dev[b, a]:1x44[ioaen] must be high to enable access to the register space, regardless of the state of this bit. 0 io enable. read only. this bit is fixed in the low state. bits description 31:8 classcode. provides the ioapic class code. 7:0 revision. bits description 31:24 bist. these bits are fixed at their default values. 23:16 header. these bits are fixed at their default values. 15:8 latency. these bits are fixed at their default values. 7:0 cache. these bits are fixed at their default values. bits description 63:12 ioabar: ioapic base address register. read-write. these bits specify the address space of the ioapic register set, ioaxx. note: bits[63:40] are required to be programmed low; setting any of these bits high results in undefined behavior. 11:0 hardwired. read only. these bits are all hardwired to their default state to indicate a 4k byte block of 64-bit, non-prefetchable memory space. bits description 31:16 subsystem id. this field controls no hardware. 15:0 subsystem vendor id. this field controls no hardware.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 65 ioapic control register dev[b, a]:1x44 default: 0000 0000h attribute: read-write. ioapic base address register dev[b, a]:1x48 offsets 10h and 48h provide access to the same 8-byte register. offset 48h is always accessible. however, off- set 10h can be disabled from read and write access through dev[b, a]:1x44[osvisbar]. see offset 10h for the register specification. 5.4 ioapic registers these registers are located in ioaxx memory space. the base address register for these registers is dev[b, a]:1x10/48. see section 5.1.2 for a description of the register naming convention. see also section 4.5.2 for more details about interrupt operation. see also dev[b, a]:0x[bc, b8] for a description of alternative access to these registers and expanded programmability. the ioapic register set supports 4 interrupts and corresponding redirection registers. the space is indexed through two memory-mapped ports: ioa00 (ioaxx at offset 00h) provides the 8-bit index register; ioa10h (ioaxx at offset 10h) provides the 32-bit data port. writes to ioa10h, the 32-bit data port, must be 32-bit, aligned accesses; other than 32-bit writes result in undefined behavior. reads provide all four bytes regardless of the byte enables. the index written to ioa00 selects one of the following: bits description 31:2 reserved. 1 ioaen: ioapic enable. 1=access to the ioapic registers pointed to by dev[b, a]:1x10/48 is enabled and the ioapic is enabled to generate interrupt requests. 0 osvisbar: operating system visible base address register. 0=dev[b, a]:1x10 is not visible; reads provide all zeros and writes are ignored. also, the state of dev[b, a]:1x04[masen, memen] are ignored. 1=the ioapic bar is read-write accessible through dev[b, a]:1x10 and dev[b, a]:1x04[masen, memen] function as specified. ioa00[7:0] description default 00h apic id register. bits[27:24] are read-write; they control no hardware. all other bits are reserved. 0000 0000h 01h ioapic version register. read only. these bits are fixed in their default state. 0003 0011h 02h ioapic arbitration id register. bits[27:24] are read-write; they control no hardware. all other bits are reserved. 0000 0000h
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 66 rdr : the redirection registers are defined as follows: 10h-17h rdr: redirection registers. each of the 4 redirection registers utilizes two indexes. bits[63:32] are accessed through the odd indexes and bits[31:0] are accessed through the even indexes. they are mapped to the pci interrupt pins as follows: pin ioa00 for bits[31:0] ioa00 for bits[63:32] [b, a]_pirqa# 10h 11h [b, a]_pirqb# 12h 13h [b, a]_pirqc# 14h 15h [b, a]_pirqd# 16h 17h bits[63:32] = 0000 0000h. bits[31:0] = 0001 0000h. 18h-ffh reserved. bits description 63:56 dest: destination. read-write. intrinfo[15:8] in the link interrupt request packet. in physical mode, bits[59:56] specify the apic id of the target processor. in logical mode bits[63:56] specify a set of processors. 55:17 reserved. 16 im: interrupt mask. read-write. 1=interrupt is masked. when the interrupt is specified to be in edge-sensitive mode and this bit transitions from 1 to 0, then no interrupt request is generated regardless of the state of the interrupt line. when the interrupt is specified to be in level-sensitive mode and the interrupt line is in the asserted state, then when this bit transitions from 1 to 0, an interrupt request is generated. the state of this bit is also used for the nioairq[d:a]# pins; see dev[b, a]:0x40[nioamode]. 15 tm: trigger mode. read-write. intrinfo[5] in the link interrupt request packet. 0=edge sensitive. 1=level sensitive. normally, it is expected that this bit be programmed for level-sensitive interrupts. note: this bit is ignored for delivery modes of smi, nmi, init, and extint, which are always treated as edge sensitive. 14 irr: interrupt request receipt. read only. this bit is not defined for edge-triggered interrupts. for level-triggered interrupts, this bit is set by the hardware after an interrupt is detected. it is cleared by receipt of eoi as specified in section 4.5.2. . 13 pol: polarity. read-write. 0=active high for level-sensitive interrupts and rising edge for edge- sensitive interrupts. 1=active low for level-sensitive interrupts and falling edge for edge-sensitive interrupts. this bit applies to the polarity of the [b, a]pirq[d:a]# pins as they enter the ic. normally, it is expected that this bit be programmed for active low interrupts. this bit has no effect on the nioairq[d, c, b, a]# pins. 12 ds: delivery status. read only. 0=idle. 1=interrupt message pending. 11 dm: destination mode. read-write. intrinfo[6] in the link interrupt request packet. 0=physical mode. 1=logical mode.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 67 5.5 shpc working registers these registers are accessed through either: ? indexed configuration space (see dev[b, a]:0x90[select] and dev[b, a]:0x94[data]), or ? non-indexed memory space (see shpc[b, a]:00). see section 5.1.2 for a description of the register naming convention. if deva:0x48[hpena] = 0 then the shpca:xx registers are all reserved; if deva:0x48[hpenb] = 0 then the shpcb:xx registers are all reserved. shpc base offset register shpc[b, a]:00 default: 0000 0000h. attribute: read only. 10:8 mt: message type. read-write. these bits are physically located in idrdr[mt] (see dev[b, a]:0x[bc, b8]). accesses to this field result in translated accesses to the register bits in idrdr[mt]. the value in idrdr[mt] becomes the intrinfo[4:2] field in link interrupt request packets. the translation is as follows: access to rdr[mt] interrupt type value in idrdr[mt] 000b fixed 000b 001b lowest priority 001b 010b smi 010b 011b reserved 111b 100b nmi 011b 101b init 100b 110b reserved 101b 111b extint 110b so, for example, a write of 111b to rdr[mt] results in a write of 110b in idrdr[mt]. subsequent reads of rdr[mt] provide 111b. subsequent reads of idrdr[mt] provide 110b. the value placed in link interrupt request packets is as specified in idrdr[mt] (110b). a write of 110b in idrdr[mt] would be read as 111b through rdr[mt]. 7:0 iv: interrupt vector. read-write. intrinfo[23:16] in the link interrupt request packet. bits description 31:0 base_offset. this register is hard-wired low to indicate that the memory-space base address of the shpc register set is specified only by dev[b,a]:0x10[shpcbar].
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 68 shpc slots available register i shpc[b, a]:04 default: 0000 0000h attribute: write once. shpc slots available register ii shpc[b, a]:08 default: 0000 0000h attribute: write once. shpc slot configuration register shpc[b, a]:0c default: 0000 0000h attribute: write once. bits description 31:29 reserved. 28:24 n_133pcix. indicates maximum number of hot plug slots available to be enabled when the bus is running at 133 mhz in pci-x ? mode. 23:21 reserved. 20:16 n_100pcix. indicates maximum number of hot plug slots available to be enabled when the bus is running at 100 mhz in pci-x ? mode. 15:13 reserved. 12:8 n_66pcix. indicates maximum number of hot plug slots available to be enabled when the bus is running at 66 mhz in pci-x ? mode. 7:5 reserved. 4:0 n_33conv. indicates maximum number of hot plug slots available to be enabled when the bus is running at 33 mhz in conventional pci mode. bits description 31:5 reserved. 4:0 n_66conv. indicates maximum number of hot plug slots available to be enabled when the bus is running at 66 mhz in conventional pci mode. bits description 31 abi: attention button implemented. 1=hot plug slots implement the attention button. 0=hot plug slots do not implement the attention button. 30 mrlsi: mrl sensor implemented. 1=hot plug slots implement the mrl sensor. 0=hot plug slots do not implement the mrl sensor. 29 psn_up: physical slot number up/down. 1=each external slot label increments by 1 from the value in shpc[b, a]:0c[psn]. 0=each external slot label decrements by 1 from the value in shpc[b, a]:0c[psn]. 28:27 reserved. 26:16 psn: physical slot number. specifies the physical slot number of the device specified by shpc[b, a]:0c[fdn]. 15:13 reserved. 12:8 fdn: first device number. specifies the device number assigned to the first hot plug slot on the secondary bridge bus.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 69 shpc secondary bus configuration register shpc[b, a]:10 default: 0100 0000h attribute: read only. shpc command register shpc[b, a]:14 writes to shpc[b, a]:14 are ignored if shpc[b, a]:16[bsy] = 1. default: 0000h attribute: read-write. decodings for shpc command code fields are: ? attention indicator and power indicator specify led states. 00b=no change; 01b=on; 10b=blink; 11b=off. ? slot state specifies the command to the slot. 00b=no change; 01b=power only; 10b=enable slot; 11b=dis- able slot. ? bus speed/mode specifies the bridge speed and mode. see shpc[b, a]:10[mode] for the encoding. 7:5 reserved. 4:0 nsi: number of slots implemented. specifies the number of hot plug slots on the bridge. bits description 31:24 shpc programming interface. identifies the format of the shpc working register set. 23:3 reserved. 2:0 mode. indicates the current speed and mode at which the secondary bridge bus operates. 000b = 33 mhz conventional mode. 001b = 66 mhz conventional mode. 010b = 66 mhz pci-x ? mode. 011b = 100 mhz pci-x ? mode. 100b = 133 mhz pci-x ? mode. 101b, 110b, and 111b are reserved. bits description 15:13 reserved. 12:8 tgt: target slot. specifies the slot to which shpc[b, a]:14[cmd] is applied for the slot operation command. 7:0 cmd: shpc command code. specifies the shpc command to be executed (see below). command name cmd[7:0] slot operation 0 0 attention indicator power indicator slot state set bus segment speed/mode01000bus speed/mode power only all slots 01001000 enable all slots 01001001
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 70 shpc status register shpc[b, a]:16 the controller command error code field consists of shpc[b, a]:16[invsm_err, invcmd_err, mrlo_err]. no bits or one bit of the controller command error code field may be updated when shpc[b, a]:16[bsy] transitions from 1 to 0, indicating command completion with an error. if a bit in the controller command error code field is set, then it remains set until the next 1 to 0 transition of bsy. default: 0000h attribute: read only. bits description 15:4 reserved. 3 invsm_err: invalid speed/mode. this is set high when one of the following errors occurs: ? the target slot specified by shpc[b, a]:14[tgt] is not capable of running at the current speed or mode when the slot operation command enable command is issued. ? a slot on the bus is not capable of running at the current bus speed or mode when the enable all slots command is issued. ? an enabled slot on the bus segment is not capable of running at the requested bus speed or mode when the set bus segment speed/mode command is issued. ? the set bus segment speed/mode command is issued when the number of slots available at the requested bus speed or mode (specified by shpc[b, a]:[08, 04]) is greater than zero and less than the number of slots enabled. 2 invcmd_err: invalid shpc command. this is set high when one of the following errors occurs: ? a reserved command code is used. ? the target slot specified by shpc[b, a]:14[tgt] is zero or is greater than the shpc[b, a]:0c[nsi] for any slot operation command. ? the target slot specified by shpc[b, a]:14[tgt] is greater than the number of slots available at the current bus speed or mode (specified by shpc[b, a]:[08, 04]) when slot operation command enable is issued. ? the target slot specified by shpc[b, a]:14[tgt] is enabled when slot operation command power only is issued. ? one or more slots on the bus segment are already enabled when power only all slots command or enable all slots command is issued. ? the set bus segment speed/mode command is issued when shpc[b, a]:[08, 04] indicate no slots are available at the requested speed or mode. 1 mrlo_err: mrl open. 1=the mrl of the target slot specified by shpc[b, a]:14[tgt] was open when slot operation command power only or slot operation command enable was issued. 0 bsy: controller busy. 1=an shpc command (see shpc[b, a]:14) is in progress.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 71 shpc interrupt locator register shpc[b, a]:18 default: 0000 0000h attribute: read only. shpc serr locator register shpc[b, a]:1c default: 0000 0000h attribute: read only. shpc serr-int register shpc[b, a]:20 the wakeup signal shown below sets dev[b, a]:0x9c[pme_sts]. shpc_wakeup = (shpc[b, a]:18[ip] != 0000b) | ~shpc[b, a]:20[cc_im] & shpc[b, a]:20[cc_sts]; the shpc interrupt shown below is routed to the [b, a]_pirqa# pin. shpc_intr = ~shpc[b, a]:20[gim] & shpc_wakeup; the shpc system error shown below sets dev[b, a]:0x1c[rse] (see also dev[b, a]:0x3c[serren]). shpc_serr = ~shpc[b, a]:20[gserrm] & ( (shpc[b, a]:1c[serrp] != 0000b) | ~shpc[b, a]:20[a_serrm] & shpc[b, a]:20[atout_sts]); bits description 31:5 reserved. 4:1 ip[4:1]: slot interrupt pending. each bit n of this field corresponds to slot n . 1=a slot status bit capable of generating interrupts is set and the corresponding interrupt mask is 0. slot status bits capable of generating interrupts are shpc[b, a]:[30, 2c, 28, 24][cpc_sts, ipf_sts, abp_sts, mrlsc_sts, cpf_sts]. the corresponding interrupt masks are shpc[b, a]:[30, 2c, 28, 24][cp_im, ipf_im, ab_im, mrls_im, cpf_im]. 0 cc_ip: command complete interrupt pending. 1=shpc[b, a]:20[cc_sts] is 1 and shpc[b, a]:20[cc_im] is 0. bits description 31:5 reserved. 4:1 serrp[4:1]: slot serr pending. each bit n of this field corresponds to slot n . 1=a slot status bit capable of generating serr is set and the corresponding serr mask is 0. slot status bits capable of generating serr are shpc[b, a]:[30, 2c, 28, 24][mrlsc_sts, cpf_sts]. the corresponding serr masks are shpc[b, a]:[30, 2c, 28, 24][mrls_serrm, cpf_serrm]. 0 a_serrp: arbiter serr pending. 1=shpc[b, a]:20[atout_sts] is 1 and shpc[b, a]:20[a_serrm] is 0.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 72 default: 0000 000fh attribute: see below. shpc logical slot registers shpc[b, a]:[30, 2c, 28, 24] the offset for the shpc logical slot register (or lsr) for slot 1 is 24h, for slot 2 is 28h, for slot 3 is 2ch, and for slot 4 is 30h. lsr is used instead of shpc[b, a]:[30, 2c, 28, 24] in the description below. see shpc[b, a]:20 for information about how these registers may affect interrupts, events, and system errors. default: 7f00 3f3fh attribute: see below. bits description 31:18 reserved. 17 atout_sts: arbiter timeout status. read; set by hardware; write 1 to clear. set when an arbiter timeout is detected by the shpc logic. the arbiter timeout occurs when the pci bus is requested (from the internal arbiter) for a hot plug operation and it is not granted for 2^23 [b, a]_pclk cycles. 16 cc_sts: command completion status. read; set by hardware; write 1 to clear. set when an shpc[b, a]:16[bsy] transition from 1 to 0 is detected. 15:4 reserved. 3 a_serrm: arbiter serr mask. read-write. 1=serr indication for arbiter timeout is disabled. 2 cc_im: command complete interrupt mask. read-write. 1=shpc interrupt generation for command completion is disabled. 1 gserrm: global serr mask. read-write. 1=serr indication is disabled. 0 gim: global interrupt mask. read-write. 1=shpc interrupt generation is disabled. bits description 31 reserved. 30 cpf_serrm: connected power fault serr mask. read-write. 1=serr generation is disabled when lsr[cpf_sts] is set. 0=serr generation is enabled when lsr[cpf_sts] is set. 29 mrls_serrm: mrl sensor serr mask. read-write. 1=serr generation is disabled when lsr[mrlsc_sts] is set. 0=serr generation is enabled when lsr[mrlsc_sts] is set. 28 cpf_im: connected power fault interrupt mask. read-write. 1=interrupt generation is disabled when lsr[cpf_sts] is set. 0=interrupt generation is enabled when lsr[cpf_sts] is set. 27 mrls_im: mrl sensor interrupt mask. read-write. 1=interrupt generation is disabled when lsr[mrlsc_sts] is set. 0=interrupt generation is enabled when lsr[mrlsc_sts] is set. 26 ab_im: attention button interrupt mask. read-write. 1=interrupt generation is disabled when lsr[abp_sts] is set. 0=interrupt generation is enabled when lsr[abp_sts] is set. 25 ipf_im: isolate power fault interrupt mask. read-write. read-write. 1=interrupt generation is disabled when lsr[ipf_sts] is set. 0=interrupt generation is enabled when lsr[ipf_sts] is set. 24 cp_im: card presence interrupt mask. read-write. 1=interrupt generation is disabled when lsr[cpc_sts] is set. 0=interrupt generation is enabled when lsr[cpc_sts] is set. 23:21 reserved. 20 cpf_sts: connected power fault status. read; set by hardware; write 1 to clear. set when lsr[pf] changes from 0 to 1 while lsr[ss] = 10b (slot is enabled).
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 73 19 mrlsc_sts: mrl sensor change status. read; set by hardware; write 1 to clear. set when lsr[mrls] changes its value. 18 abp_sts: attention button press status. read; set by hardware; write 1 to clear. set when lsr[ab] transitions from 0 to 1. 17 ipf_sts: isolated power fault status. read; set by hardware; write 1 to clear. set when lsr[pf] changes from 0 to 1 while lsr[ss] != 10b (slot is not in the enabled state). . 16 cpc_sts: card presence change status. read; set by hardware; write 1 to clear. set when lsr[prsnt1_2] field changes value. 15:14 reserved. 13:12 pci-x _cap: pci-x ? capability. read-only. reflects the current pci-x ? capability of the add-in- card. these bits are not valid if the slot is empty. 00b = conventional pci. 01b = 66 mhz pci-x ? mode. 10b = reserved. 11b = 133 mhz pci-x ? mode. 11:10 prsnt1_2: prsnt1#/prsnt2#. read-only. reflects the current debounced state of the prsnt1# and prsnt2# pins on the slot. 00b = card present; 7.5w. 01b = card present; 15w. 10b = card present; 25w. 11b = slot empty. 9 m66_cap: 66 mhz capable. read-only. this bit is valid only when the slot is occupied and powered. 1=add-in card is capable of running at 66 mhz conventional mode. 0=add-in-card is capable of running at 33 mhz conventional mode only. 8 mrls: mrl sensor. read-only. reflects the current state of the debounced mrl sensor. 1=mrl sensor is open. 0=mrl sensor is closed. 7 ab: attention button. read-only. reflects the current state of the debounced attention button. 1=attention button is being pressed. 0=attention button is released. 6 pf: power fault. read-only. reflects the current state of the power fault latch in the slot power control circuitry. 1=power fault (isolated or connected) is detected. 5:4 ais: attention indicator state. read-only. reflects the current state of the attention indicator. 00b = reserved. 01b = on. 10b = blink. 11b = off. 3:2 pis: power indicator state. read-only. reflects the cuttent state of the power indicator. 00b = reserved. 01b = on. 10b = blink. 11b = off. 1:0 ss: slot state. read-only. reflects the current state of the slot. 00b = reserved. 01b = powered only. 10b = enabled. 11b = disabled.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 74 6 electrical data 6.1 absolute ratings the ic is not designed to operate beyond the parameters shown in the following table. 6.2 operating ranges the ic is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in the following table. parameter minimum maximum comments vdd12[b, a] C0.5 v 1.7 v vdd18, vdda18 C0.5 v 2.0 v vdd33 C0.5 v 3.6 v t case (under bias)85 c t storage -65 c150 c table 11: absolute maximum ratings. parameter minimum typical maximum units comments vdd12[b, a] 1.14 1.2 1.26 v vdd18, vdda18 1.71 1.8 1.89 v vdda18 peak-to-peak noise 50 mv maximum sinusoidal amplitude at frequency range from 50 khz to 20 mhz. vdd33 3.135 3.3 3.465 v t case (under bias)85 deg c table 12: operating ranges.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 75 6.3 dc characteristics see the hypertransport tm technology electrical specification for the dc characteristics of link signals. the following table shows current consumption in amps and power in watts for each power plane. unless oth- erwise noted, values assume that both bridges are operating at 133 mhz. the following table shows dc characteristics for signals on the vdd33 power plane. typical max parameter description current power current power vdd12a current, power 0.13 a 0.16 w 0.19 a 0.24 w vdd12b current, power 0.07 a 0.08 w 0.09 a 0.12 w vdd18 current, power; operational 1.90 a 3.42 w 2.40 a 4.54 w vdd18 current, power; internal clock gated mode (see section 4.3.3); both bridges operating at 66 mhz. 0.30 a 0.54 w 0.43 a 0.82 w vdd18 current, power; internal clock gated mode (see section 4.3.3); both bridges operating at 133 mhz. 0.52 a 0.94 w 0.75 a 1.42 w vdda18 current, power 0.02 a 0.04 w 0.03 a 0.06 w vdd33 current, power; assumes no current load on pci bus signals 0.50 a 1.65 w 0.60 a 2.08 w total power; operational (no clock gating) 5.4 w 7.0 w table 13: current and power consumption. symbol parameter description min max units comments v il input low voltage -0.5 0.35 vdd33 v v ih input high voltage 0.5 vdd33 0.5 + vdd33 v v ol output low voltage; i out = 1.5 ma 0.1 vdd33 v v oh output high voltage; i out = -0.5 ma 0.9 vdd33 v i li input leakage current +/- 10 ua c in input capacitance 8 pf v xcl [b, a]_pcixcap voltage for low state 0.15 vdd33 v v xcm [b, a]_pcixcap voltage for mid state 0.25 vdd33 0.70 vdd33 v v xch [b, a]_pcixcap voltage for high state 0.85 vdd33 v table 14: dc characteristics for signals on the vdd33 power plane.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 76 6.4 ac characteristics see the hypertransport technology electrical specification for the ac characteristics of link signals, pwrok, reset#, and ldtstop#. the following table shows ac requirements for refclk. the following table shows ac specification data for pci clocks. the following table shows general ac specification data. pclk refers to [b, a]_pclk[4:0]. symbol parameter description min max units comments t ref refclk cycle time 15 18 ns t refcj refclk cycle to cycle jitter; difference in the period of any two adjacent refclk cycles 0.250 ns t refpj refclk period jitter; difference between the nominal period and the period of any refclk cycle -0.300 +0.300 ns t refsw refclk slew rate 1 4 v/ns t refss refclk 33 khz spread spectrum frequency change from t ref -0.5 0 % table 15: ac requirements for refclk. symbol parameter description 133 mhz 100 mhz 66 mhz 33 mhz units comments min max min max min max min max t cyc [b, a]_pclk[4:0] cycle time 7.5 10 15 30 ns t high [b, a]_pclk[4:0] high time34611ns t low [b, a]_pclk[4:0] low time34611ns t slew [b, a]_pclk[4:0] slew rate 1.5 4 1.5 4 1.5 4 1.5 4 v/ns table 16: ac data for pci clocks. symbol parameter description pci-x ? 133, 100, 66 mhz conven- tional pci 66 mhz conven- tional pci 33 mhz units comments min max min max min max t val pclk to signal valid delay 0.73.826211ns t on pclk to signal active delay 022ns t off pclk to signal float delay 7 14 28 ns t su input setup time to pclk 1.2 3 7 ns t h input hold time from pclk 0.5 0 0 ns table 17: ac data for pci bus.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 77 7 ball designations top side view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 a ldt comp1 vss vss ltaca d_p0 ltaca d_n0 ltaca d_p2 ltaca d_n2 ltacl k0_p ltacl k0_n ltaca d_p5 ltaca d_n5 ltaca d_p7 ltaca d_n7 lract l_n lract l_p lraca d_n6 lraca d_p6 lraca d_n4 lraca d_p4 lraca d_n3 lraca d_p3 lraca d_n1 lraca d_p1 vss cmp ovr a b ldt comp2 vss ldt comp0 vss vss ltaca d_p1 vdd18 ltaca d_p3 vss ltaca d_p4 vdd18 ltaca d_p6 vss ltact l_p0 vdd18 lraca d_n7 vss lraca d_n5 vdd18 lracl k0_n vss lraca d_n2 vdd18 lraca d_n0 vss strap l2 reset # b c vss vss ldt comp3 vss vss ltaca d_n8 ltaca d_n1 ltaca d_n10 ltaca d_n3 ltacl k1_n ltaca d_n4 ltaca d_n13 ltaca d_n6 ltaca d_n15 ltact l_n0 rsvd3 lraca d_p7 lraca d_p14 lraca d_p5 lraca d_p12 lracl k0_p lraca d_p11 lraca d_p2 lraca d_p9 lraca d_p0 vss ldt stop# pwr ok ref clk c d free 12 free 10 vss free1 vss ltaca d_p8 vdd18 ltaca d_p10 vss ltacl k1_p vdd18 ltaca d_p13 vss ltaca d_p15 vdd18 rsvd2 vss lraca d_n14 vdd18 lraca d_n12 vss lraca d_n11 vdd18 lraca d_n9 vss vss test vss vss d e free 18 free 19 free 13 free 14 vss ltaca d_p9 ltaca d_n9 ltaca d_p11 ltaca d_n11 ltaca d_p12 ltaca d_n12 ltaca d_p14 ltaca d_n14 rsvd0 rsvd1 lraca d_n15 lraca d_p15 lraca d_n13 lraca d_p13 lracl k1_n lracl k1_p lraca d_n10 lraca d_p10 lraca d_n8 lraca d_p8 vss vss vss ltbca d_p0 e f b_ad 35 b_ad 34 b_ad 33 b_ad 32 free5 vss vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 nioa irqa# vss ltbca d_n1 ltbca d_p1 ltbca d_n0 f g b_ad 38 vss b_ad 37 vdd33 b_ad 36 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 nioa irqb# nioa irqd# nioa irqc# vss vdd18 ltbca d_p2 g h b_ad 44 b_ad 43 b_ad 42 b_ad 41 b_ad 40 b_ad 39 vss vdd18 vss vdd12 a vss vdd18 vss vdd18 vss vdd18 vss vdd12 a vss vdd18 vss vdd18 vss vdd33 strap l3 vdd18 ltbca d_n3 ltbca d_p3 ltbca d_n2 h j b_ad 50 b_ad 49 b_ad 48 b_ad 47 b_ad 46 b_ad 45 vdd33 vss vdd33 vss vdd12 a vss vdd18 vss vdd18 vss vdd12 a vss vdd18 vss vdd18 vss vdd18 vss hpsod hpsil# rsvd4 vss ltbcl k0_p j k b_ad 53 vss b_ad 52 vdd33 b_ad 51 vdd33 vss vdd33 vss vdd12 a vss vdd18 vss vdd18 vss vdd18 vss vdd12 a vss vdd18 vss vdd18 vss a_com pat rsvd5 vss ltbca d_n4 ltbca d_p4 ltbcl k0_n k l b_ad 59 b_ad 58 b_ad 57 b_ad 56 b_ad 55 b_ad 54 vdd33 vss vdd33 vss vdd12 a vss vdd18 vss vdd18 vss vdd12 a vss vdd12 b vss vdd12 b vss vdd18 rsvd6 rsvd7 a_req 4# rsvd8 vdd18 ltbca d_p5 l m b_cbe _l4 b_par 64 b_ad 63 b_ad 62 b_ad 61 b_ad 60 vss vdd33 vss vdd33 vss vdd18 vss vdd18 vss vdd18 vss vdd12 b vss vdd12 b vss vdd18 vss a_pll clko a_pll clki vdd18 ltbca d_n6 ltbca d_p6 ltbca d_n5 m n b_cbe _l7 vss b_cbe _l6 vdd33 b_cbe _l5 vss vdd33 vss vdd33 vss vdd33 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 a_gnt 4# a_ pclk4 rsvd9 rsvd 10 vss ltbca d_p7 n p b_ad3 b_ad2 b_ad1 b_ad0 b_ack 64# b_req 64# vss vdd33 vss vdd33 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss a_ pclk3 a_gnt 3# vss ltbct l_n ltbct l_p ltbca d_n7 p r b_ad4 b_ad5 b_ad6 b_ad7 b_cbe _l0 b_ad8 vdd33 vss vdd33 vss vdd33 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 a_ pclk2 a_gnt 2# a_req 3# rsvd 11 vdd18 lrbct l_n r t b_ad9 vss b_m66 en vdd33 b_ad 10 vdd33 vss vdd33 vss vdd33 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss a_ pclk1 a_req 2# vdd18 lrbca d_p7 lrbca d_n7 lrbct l_p t u b_ad1 1 b_ad 12 b_ad 13 b_ad 14 b_ad 15 b_cbe _l1 vdd33 vss vdd33 vss vdd33 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 vss vdd18 a_pirq a# a_gnt 1# rsvd 12 rsvd 13 vss lrbca d_n6 u v b_par b_ serr# b_ perr# b_ stop# b_pcix cap b_dev sel# vss vdd33 vss vdd33 vss vdd18 vss vdd18 vss vdd18 vss vdd12 b vss vdd12 b vss vdd18 vss a_req 1# a_pirq b# vss lrbca d_p5 lrbca d_n5 lrbca d_p6 v w b_ trdy# vss b_irdy # vdd33 b_fra me# vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd12 b vss vdd12 b vss vdd18 rsvd 14 rsvd 15 rsvd 16 rsvd 17 vdd18 lrbca d_n4 w y b_cbe _l2 b_ad 16 b_ad 17 b_ad 18 b_ad 19 b_ad 20 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd18 rsvd 18 vdd18 lrbcl k0_p lrbcl k0_n lrbca d_p4 y aa b_ad 21 b_ad 22 b_ad 23 b_cbe _l3 b_ad 24 b_ad 25 vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd18 a_pirq c# rsvd 19 rsvd 20 rsvd 21 vss lrbca d_n3 aa ab b_ad 26 vss b_ad 27 vdd33 b_ad 28 vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss a_ pclk0 a_pirq d# vss lrbca d_p2 lrbca d_n2 lrbca d_p3 ab ac b_ad 29 b_ad 30 b_ad 31 b_req 0# b_gnt 0# b_ pclk0 vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 vss vdd33 a_req 0# a_gnt 0# a_pre set# rsvd 22 vdd18 lrbca d_n1 ac ad b_pre set# b_pirq d# b_pirq c# b_pirq b# free6 b_pme # a_pme # vss free 15 free8 a_ad 33 vdd33 a_ad 42 a_ad 48 vss a_ad6 2 a_cbe _l7 vdd33 a_ad6 a_ad 10 vss a_ perr# a_fra me# vdd33 a_ad 23 vdd18 lrbca d_p0 lrbca d_n0 lrbca d_p1 ad ae b_pirq a# vss p_cal vdd33 free 17 b_pll clki b_pll clko b_req 4# free 22 vss a_ad 34 a_ad 39 a_ad 43 a_ad 49 a_ad 54 a_ad 61 a_cbe _l6 a_ad0 a_ad5 a_m66 en a_ad 13 a_ serr# a_irdy # a_ad 17 a_ad 22 vss vss vss vss ae af b_req 1# p_cal # b_gnt 1# b_ pclk1 vdd33 b_req 2# b_req 3# vdd33 b_ pclk4 vss a_ad 35 vdd33 a_ad 44 a_ad 50 vdd33 a_ad 60 a_cbe _l5 vdd33 a_ad4 a_ad9 vdd33 a_par a_ trdy# vdd33 a_ad 21 a_ad 26 vdd33 a_ad 31 vdda 18 af ag free 16 free 20 vdd33 nc0 nc1 b_gnt 2# b_gnt 3# b_gnt 4# free3 vss a_ad 36 a_ad 40 a_ad 45 a_ad 51 a_ad 55 a_ad 59 a_cbe _l4 a_ack 64# a_ad3 a_ad8 a_ad 12 a_cbe _l1 a_dev sel# a_ad 16 a_ad 20 a_ad 25 a_ad 28 a_ad 30 vdda 18 ag ah vss nc2 nc3 vss b_ pclk2 b_ pclk3 vss vss vss a_ad 37 vss a_ad 46 a_ad 52 vss a_ad 58 a_par 64 vss a_ad2 a_cbe _l0 vss a_ad 15 a_pcix cap vss a_ad 19 a_ad 24 vss a_ad 29 ah aj free9 free 21 free2 hpsic hpsoc free4 free7 a_ad 32 a_ad 38 a_ad 41 a_ad 47 a_ad 53 a_ad 56 a_ad 57 a_ad 63 a_req 64# a_ad1 a_ad7 a_ad1 1 a_ad 14 a_ stop# a_cbe _l2 a_ad 18 a_cbe _l3 a_ad 27 aj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 figure 13: ball designations.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 78 alphabetical listing of signals and corresponding bga designators. signal name ball signal name ball signal name ball signal name ball a_ack64# ag18 a_ad51 ag14 a_req4# l26 b_ad46 j5 a_ad0 ae18 a_ad52 ah14 a_req64# aj18 b_ad47 j4 a_ad1 aj19 a_ad53 aj14 a_serr# ae22 b_ad48 j3 a_ad2 ah19 a_ad54 ae15 a_stop# aj23 b_ad49 j2 a_ad3 ag19 a_ad55 ag15 a_trdy# af23 b_ad50 j1 a_ad4 af19 a_ad56 aj15 b_ack64# p5 b_ad51 k5 a_ad5 ae19 a_ad57 aj16 b_ad0 p4 b_ad52 k3 a_ad6 ad19 a_ad58 ah16 b_ad1 p3 b_ad53 k1 a_ad7 aj20 a_ad59 ag16 b_ad2 p2 b_ad54 l6 a_ad8 ag20 a_ad60 af16 b_ad3 p1 b_ad55 l5 a_ad9 af20 a_ad61 ae16 b_ad4 r1 b_ad56 l4 a_ad10 ad20 a_ad62 ad16 b_ad5 r2 b_ad57 l3 a_ad11 aj21 a_ad63 aj17 b_ad6 r3 b_ad58 l2 a_ad12 ag21 a_cbe_l0 ah20 b_ad7 r4 b_ad59 l1 a_ad13 ae21 a_cbe_l1 ag22 b_ad8 r6 b_ad60 m6 a_ad14 aj22 a_cbe_l2 aj24 b_ad9 t1 b_ad61 m5 a_ad15 ah22 a_cbe_l3 aj26 b_ad10 t5 b_ad62 m4 a_ad16 ag24 a_cbe_l4 ag17 b_ad11 u1 b_ad63 m3 a_ad17 ae24 a_cbe_l5 af17 b_ad12 u2 b_cbe_l0 r5 a_ad18 aj25 a_cbe_l6 ae17 b_ad13 u3 b_cbe_l1 u6 a_ad19 ah25 a_cbe_l7 ad17 b_ad14 u4 b_cbe_l2 y1 a_ad20 ag25 a_compat k24 b_ad15 u5 b_cbe_l3 aa4 a_ad21 af25 a_devsel# ag23 b_ad16 y2 b_cbe_l4 m1 a_ad22 ae25 a_frame# ad23 b_ad17 y3 b_cbe_l5 n5 a_ad23 ad25 a_gnt0# ac25 b_ad18 y4 b_cbe_l6 n3 a_ad24 ah26 a_gnt1# u25 b_ad19 y5 b_cbe_l7 n1 a_ad25 ag26 a_gnt2# r25 b_ad20 y6 b_devsel# v6 a_ad26 af26 a_gnt3# p25 b_ad21 aa1 b_frame# w5 a_ad27 aj27 a_gnt4# n24 b_ad22 aa2 b_gnt0# ac5 a_ad28 ag27 a_irdy# ae23 b_ad23 aa3 b_gnt1# af3 a_ad29 ah28 a_m66en ae20 b_ad24 aa5 b_gnt2# ag6 a_ad30 ag28 a_par af22 b_ad25 aa6 b_gnt3# ag7 a_ad31 af28 a_par64 ah17 b_ad26 ab1 b_gnt4# ag8 a_ad32 aj10 a_pcixcap ah23 b_ad27 ab3 b_irdy# w3 a_ad33 ad11 a_pclk0 ab24 b_ad28 ab5 b_m66en t3 a_ad34 ae11 a_pclk1 t24 b_ad29 ac1 b_par v1 a_ad35 af11 a_pclk2 r24 b_ad30 ac2 b_par64 m2 a_ad36 ag11 a_pclk3 p24 b_ad31 ac3 b_pcixcap v5 a_ad37 ah11 a_pclk4 n25 b_ad32 f4 b_pclk0 ac6 a_ad38 aj11 a_perr# ad22 b_ad33 f3 b_pclk1 af4 a_ad39 ae12 a_pirqa# u24 b_ad34 f2 b_pclk2 ah6 a_ad40 ag12 a_pirqb# v25 b_ad35 f1 b_pclk3 ah7 a_ad41 aj12 a_pirqc# aa24 b_ad36 g5 b_pclk4 af9 a_ad42 ad13 a_pirqd# ab25 b_ad37 g3 b_perr# v3 a_ad43 ae13 a_pllclki m25 b_ad38 g1 b_pirqa# ae1 a_ad44 af13 a_pllclko m24 b_ad39 h6 b_pirqb# ad4 a_ad45 ag13 a_pme# ad7 b_ad40 h5 b_pirqc# ad3 a_ad46 ah13 a_preset# ac26 b_ad41 h4 b_pirqd# ad2 a_ad47 aj13 a_req0# ac24 b_ad42 h3 b_pllclki ae6 a_ad48 ad14 a_req1# v24 b_ad43 h2 b_pllclko ae7 a_ad49 ae14 a_req2# t25 b_ad44 h1 b_pme# ad6 a_ad50 af14 a_req3# r26 b_ad45 j6 b_preset# ad1 table 18: alphabetical listing of signals a_ack64# to b_preset#.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 79 signal name ball signal name ball signal name ball signal name ball signal name ball b_req0# ac4 lracad_n12 d20 ltacad_n6 c13 nc0 ag4 vdd12b v20 b_req1# af1 lracad_n13 e18 ltacad_n7 a15 nc1 ag5 vdd12b w19 b_req2# af6 lracad_n14 d18 ltacad_n8 c6 nc2 ah3 vdd12b w21 b_req3# af7 lracad_n15 e16 ltacad_n9 e7 nc3 ah4 vdd18 aa23 b_req4# ae8 lracad_p0 c25 ltacad_n1 0 c8 nioairqa# f25 vdd18 ac28 b_req64# p6 lracad_p1 a25 ltacad_n1 1 e9 nioairqb# g24 vdd18 ad26 b_serr# v2 lracad_p2 c23 ltacad_n1 2 e11 nioairqc# g26 vdd18 b12 b_stop# v4 lracad_p3 a23 ltacad_n1 3 c12 nioairqd# g25 vdd18 b16 b_trdy# w1 lracad_p4 a21 ltacad_n1 4 e13 p_cal ae3 vdd18 b20 cmpovr a27 lracad_p5 c19 ltacad_n1 5 c14 p_cal# af2 vdd18 b24 free1 d4 lracad_p6 a19 lta cad_p0 a6 pwrok c28 vdd18 b8 free2 aj5 lracad_p7 c17 lta cad_p1 b7 refclk c29 vdd18 d11 free3 ag9 lracad_p8 e25 lta cad_p2 a8 reset# b28 vdd18 d15 free4 aj8 lracad_p9 c24 lta cad_p3 b9 rsvd0 e14 vdd18 d19 free5 f5 lracad_p10 e23 lta cad_p4 b11 rsvd1 e15 vdd18 d23 free6 ad5 lracad_p11 c22 lta cad_p5 a12 rsvd2 d16 vdd18 d7 free7 aj9 lracad_p12 c20 lta cad_p6 b13 rsvd3 c16 vdd18 f10 free8 ad10 lracad_p13 e19 lta cad_p7 a14 rsvd4 j27 vdd18 f12 free9 aj3 lracad_p14 c18 lta cad_p8 d6 rsvd5 k25 vdd18 f14 free10 d2 lracad_p15 e17 lta cad_p9 e6 rsvd6 l24 vdd18 f16 free12 d1 lraclk0_n b21 lta cad_p10 d8 rsvd7 l25 vdd18 f18 free13 e3 lraclk0_p c21 lta cad_p11 e8 rsvd8 l27 vdd18 f20 free14 e4 lraclk1_n e20 lta cad_p12 e10 rsvd9 n26 vdd18 f22 free15 ad9 lraclk1_p e21 lta cad_p13 d12 rsvd10 n27 vdd18 f24 free16 ag1 lractl_n a16 lta cad_p14 e12 rsvd11 r27 vdd18 f8 free17 ae5 lractl_p a17 lta cad_p15 d14 rsvd12 u26 vdd18 g11 free18 e1 lrbcad_n0 ad28 lta clk0_n a11 rsvd13 u27 vdd18 g13 free19 e2 lrbcad_n1 ac29 lta clk0_p a10 rsvd14 w24 vdd18 g15 free20 ag2 lrbcad_n2 ab28 lta clk1_n c10 rsvd15 w25 vdd18 g17 free21 aj4 lrbcad_n3 aa29 lta clk1_p d10 rsvd16 w26 vdd18 g19 free22 ae9 lrbcad_n4 w29 lta ctl_n0 c15 rsvd17 w27 vdd18 g21 hpsic aj6 lrbcad_n5 v28 lta ctl_p0 b15 rsvd18 y25 vdd18 g23 hpsil# j26 lrbcad_n6 u29 ltbcad_n0 f29 rsvd19 aa25 vdd18 g28 hpsoc aj7 lrbcad_n7 t28 ltbcad_n1 f27 rsvd20 aa26 vdd18 g7 hpsod j25 lrbcad_p0 ad27 ltbcad_n2 h29 rsvd21 aa27 vdd18 g9 ldtcomp0 b4 lrbcad_p1 ad29 ltbcad_n3 h27 rsvd22 ac27 vdd18 h12 ldtcomp1 a3 lrbcad_p2 ab27 ltbcad_n4 k27 strapl2 b27 vdd18 h14 ldtcomp2 b2 lrbcad_p3 ab29 ltbcad_n5 m29 strapl3 h25 vdd18 h16 ldtcomp3 c3 lrbcad_p4 y29 ltbcad_n6 m27 test d27 vdd18 h20 ldtstop# c27 lrbcad_p5 v27 ltbcad_n7 p29 vdd12a h10 vdd18 h22 lracad_n0 b25 lrbcad_p6 v29 ltbcad_p0 e29 vdd12a h18 vdd18 h26 lracad_n1 a24 lrbcad_p7 t27 ltbcad_p1 f28 vdd12a j11 vdd18 h8 lracad_n2 b23 lrbclk0_n y28 ltbcad_p2 g29 vdd12a j17 vdd18 j13 lracad_n3 a22 lrbclk0_p y27 ltbcad_p3 h28 vdd12a k10 vdd18 j15 lracad_n4 a20 lrbctl_n r29 ltbcad_p4 k28 vdd12a k18 vdd18 j19 lracad_n5 b19 lrbctl_p t29 ltbcad_p5 l29 vdd12a l11 vdd18 j21 lracad_n6 a18 ltacad_n0 a7 ltbcad_p6 m28 vdd12a l17 vdd18 j23 table 19: alphabetical listing of signals b_req0# to vdd18.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 80 lracad_n7 b17 ltacad_n1 c7 ltbcad_p7 n29 vdd12b l19 vdd18 k12 lracad_n8 e24 ltacad_n2 a9 ltbclk0_n k29 vdd12b l21 vdd18 k14 lracad_n9 d24 ltacad_n3 c9 ltbclk0_p j29 vdd12b m18 vdd18 k16 lracad_n10 e22 ltacad_n4 c11 ltbctl_n p27 vdd12b m20 vdd18 k20 lracad_n11 d22 ltacad_n5 a13 ltbctl_p p28 vdd12b v18 vdd18 k22 signal name ball signal name ball signal name ball signal name ball signal name ball signal name ball signal name ball vdd18 l13 vdd33 aa17 vdd33 p8 vss ab7 vss d3 vss k19 vss r8 vdd18 l15 vdd33 aa19 vdd33 r11 vss ab9 vss d5 vss k2 vss t11 vdd18 l23 vdd33 aa21 vdd33 r7 vss ac10 vss d9 vss k21 vss t13 vdd18 l28 vdd33 aa7 vdd33 r9 vss ac12 vss e26 vss k23 vss t15 vdd18 m12 vdd33 aa9 vdd33 t10 vss ac14 vss e27 vss k26 vss t17 vdd18 m14 vdd33 ab10 vdd33 t4 vss ac16 vss e28 vss k7 vss t19 vdd18 m16 vdd33 ab12 vdd33 t6 vss ac18 vss e5 vss k9 vss t2 vdd18 m22 vdd33 ab14 vdd33 t8 vss ac20 vss f11 vss l10 vss t21 vdd18 m26 vdd33 ab16 vdd33 u11 vss ac22 vss f13 vss l12 vss t23 vdd18 n13 vdd33 ab18 vdd33 u7 vss ac8 vss f15 vss l14 vss t7 vdd18 n15 vdd33 ab20 vdd33 u9 vss ad15 vss f17 vss l16 vss t9 vdd18 n17 vdd33 ab22 vdd33 v10 vss ad21 vss f19 vss l18 vss u10 vdd18 n19 vdd33 ab4 vdd33 v8 vss ad8 vss f21 vss l20 vss u12 vdd18 n21 vdd33 ab6 vdd33 w11 vss ae10 vss f23 vss l22 vss u14 vdd18 n23 vdd33 ab8 vdd33 w13 vss ae2 vss f26 vss l8 vss u16 vdd18 p12 vdd33 ac11 vdd33 w15 vss ae26 vss f6 vss m11 vss u18 vdd18 p14 vdd33 ac13 vdd33 w17 vss ae27 vss f7 vss m13 vss u20 vdd18 p16 vdd33 ac15 vdd33 w4 vss ae28 vss f9 vss m15 vss u22 vdd18 p18 vdd33 ac17 vdd33 w7 vss ae29 vss g10 vss m17 vss u28 vdd18 p20 vdd33 ac19 vdd33 w9 vss af10 vss g12 vss m19 vss u8 vdd18 p22 vdd33 ac21 vdd33 y10 vss ag10 vss g14 vss m21 vss v11 vdd18 r13 vdd33 ac23 vdd33 y12 vss ah10 vss g16 vss m23 vss v13 vdd18 r15 vdd33 ac7 vdd33 y14 vss ah12 vss g18 vss m7 vss v15 vdd18 r17 vdd33 ac9 vdd33 y16 vss ah15 vss g2 vss m9 vss v17 vdd18 r19 vdd33 ad12 vdd33 y18 vss ah18 vss g20 vss n10 vss v19 vdd18 r21 vdd33 ad18 vdd33 y20 vss ah2 vss g22 vss n12 vss v21 vdd18 r23 vdd33 ad24 vdd33 y22 vss ah21 vss g27 vss n14 vss v23 vdd18 r28 vdd33 ae4 vdd33 y8 vss ah24 vss g6 vss n16 vss v26 vdd18 t12 vdd33 af12 vdd33 h24 vss ah27 vss g8 vss n18 vss v7 vdd18 t14 vdd33 af15 vdda18 af29 vss ah5 vss h11 vss n2 vss v9 vdd18 t16 vdd33 af18 vdda18 ag29 vss ah8 vss h13 vss n20 vss w10 vdd18 t18 vdd33 af21 vss a26 vss ah9 vss h15 vss n22 vss w12 vdd18 t20 vdd33 af24 vss a4 vss b10 vss h17 vss n28 vss w14 vdd18 t22 vdd33 af27 vss a5 vss b14 vss h19 vss n6 vss w16 vdd18 t26 vdd33 af5 vss aa10 vss b18 vss h21 vss n8 vss w18 vdd18 u13 vdd33 af8 vss aa12 vss b22 vss h23 vss p11 vss w2 vdd18 u15 vdd33 ag3 vss aa14 vss b26 vss h7 vss p13 vss w20 vdd18 u17 vdd33 g4 vss aa16 vss b3 vss h9 vss p15 vss w22 vdd18 u19 vdd33 j7 vss aa18 vss b5 vss j10 vss p17 vss w6 vdd18 u21 vdd33 j9 vss aa20 vss b6 vss j12 vss p19 vss w8 vdd18 u23 vdd33 k4 vss aa22 vss c1 vss j14 vss p21 vss y11 vdd18 v12 vdd33 k6 vss aa28 vss c2 vss j16 vss p23 vss y13 vdd18 v14 vdd33 k8 vss aa8 vss c26 vss j18 vss p26 vss y15 vdd18 v16 vdd33 l7 vss ab11 vss c4 vss j20 vss p7 vss y17 vdd18 v22 vdd33 l9 vss ab13 vss c5 vss j22 vss p9 vss y19 table 20: alphabetical listing of signals vdd18 to vss. table 19: alphabetical listing of signals b_req0# to vdd18.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 81 vdd18 w23 vdd33 m10 vss ab15 vss d13 vss j24 vss r10 vss y21 vdd18 w28 vdd33 m8 vss ab17 vss d17 vss j28 vss r12 vss y23 vdd18 y24 vdd33 n11 vss ab19 vss d21 vss j8 vss r14 vss y7 vdd18 y26 vdd33 n4 vss ab2 vss d25 vss k11 vss r16 vss y9 vdd33 aa11 vdd33 n7 vss ab21 vss d26 vss k13 vss r18 vdd33 aa13 vdd33 n9 vss ab23 vss d28 vss k15 vss r20 vdd33 aa15 vdd33 p10 vss ab26 vss d29 vss k17 vss r22 table 20: alphabetical listing of signals vdd18 to vss.
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 82 8 package specification figure 14: package mechanical drawing. ( ) d3/e3 ccc bbb a1 a2 d/e symbol d2/e2 d1/e1 package ?b m amd n aaa top view 3. this corner which consists of a triangle on both sides 2. dimensioning and tolerancing per asme-y14.5m-1994. 1. all dimensions are specified in millimeters (mm). handling and orientation purposes. of the package identifies ball a1 corner and can be used for 4. symbol "m" determines ball matrix size and "n" is number of balls. 5. dimension "b" is measured at maximum solder ball diameter on a plane parallel to datum c. 7. the following features are not shown on drawings: a) marking on die, label on package c) die and passive fudicials 6. "x" in front of package variation denotes non-qualified package per amd 01-002.3. b) laser elements general notes e e a bottom view not to scale a1 corner d d1 1.2 1.0 0.125 0.25 0.2 829 1.27 bsc 0.6 29 0.9 see notes 35.56 bsc. variations xolf829 22.80 3.35 0.5 32.30 37.3 min. 3.67 0.7 23.20 32.70 37.7 max. ?b (nx plcs) e e1 lid a2 side view a1 a e2 d2 d3 e3
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 83 9test the ic includes the following test modes. 9.1 high impedance mode in high-impedance mode, all the signals of the ic are placed into the high-impedance state. 9.2 nand tree mode there are several nand trees in the ic. some of the inputs are differential (e.g., lr[b, a] pins); for these, the _p and _n pairs of signals are converted into a single signal that is part of the nand tree, as shown in signal_3 in the following diagram. mode test a_req2# a_req1# a_req0# notes operational 0 x x x high impedance 1 0 0 0 nand tree 1 0 0 1 table 21: test modes. figure 15: nand tree. nand tree mode to output signal output signal signal_41 signal_3_p signal_2 signal_1 vdd 1 0 signal_3_n + -
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 84 nand tree 1: output signal is b_req[3]#. however, the gate connected to the last signal in this nand tree (ldtcomp[3]) is an and gate rather than a nand gate; so the expected output of this nand tree is inverted compared to the other nand trees. nand tree 2: output signal is b_req[2]#. 1 lrbclk0_[p,n] 11 ltbclk0_p 21 ltbcad_p[4] 31 ldtcomp[2] 2 lrbcad_[p,n][0] 12 ltbclk0_n 22 ltbcad_n[4] 32 ldtcomp[3] 3 lrbcad_[p,n][1] 13 ltbcad_p[0] 23 ltbcad_p[5] 4 lrbcad_[p,n][2] 14 ltbcad_n[0] 24 ltbcad_n[5] 5 lrbcad_[p,n][3] 15 ltbcad_p[1] 25 ltbcad_p[6] 6 lrbcad_[p,n][4] 16 ltbcad_n[1] 26 ltbcad_n[6] 7 lrbcad_[p,n][5] 17 ltbcad_p[2] 27 ltbcad_p[7] 8 lrbcad_[p,n][6] 18 ltbcad_n[2] 28 ltbcad_n[7] 9 lrbcad_[p,n][7] 19 ltbcad_p[3] 29 ltbctl_p 10 lrbctl_[p,n] 20 ltbcad_n[3] 30 ltbctl_n 1 lraclk0_[p,n] 21 ltaclk0_n 41 ltacad_n[4] 2 lraclk1_[p,n] 22 ltaclk1_p 42 ltacad_p[12] 3 lracad_[p,n][0] 23 ltaclk1_n 43 ltacad_n[12] 4 lracad_[p,n][8] 24 ltacad_p[0] 44 ltacad_p[5] 5 lracad_[p,n][1] 25 ltacad_n[0] 45 ltacad_n[5] 6 lracad_[p,n][9] 26 ltacad_p[8] 46 ltacad_p[13] 7 lracad_[p,n][2] 27 ltacad_n[8] 47 ltacad_n[13] 8 lracad_[p,n][10] 28 ltacad_p[1] 48 ltacad_p[6] 9 lracad_[p,n][3] 29 ltacad_n[1] 49 ltacad_n[6] 10 lracad_[p,n][11] 30 ltacad_p[9] 50 ltacad_p[14] 11 lracad_[p,n][4] 31 ltacad_n[9] 51 ltacad_n[14] 12 lracad_[p,n][12] 32 ltacad_p[2] 52 ltacad_p[7] 13 lracad_[p,n][5] 33 ltacad_n[2] 53 ltacad_n[7] 14 lracad_[p,n][13] 34 ltacad_p[10] 54 ltacad_p[15] 15 lracad_[p,n][6] 35 ltacad_n[10] 55 ltacad_n[15] 16 lracad_[p,n][14] 36 ltacad_p[3] 56 ltac tl_p 17 lracad_[p,n][7] 37 ltacad_n[3] 57 ltac tl_n 18 lracad_[p,n][15] 38 ltacad_p[11] 19 lractl_[p,n] 39 ltacad_n[11] 20 ltaclk0_p 40 ltacad_p[4]
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 85 nand tree 3: output signal is b_req[1]#. 1 b_ad[32] 22 b_ad[54] 43 b_ad[3] 64 b_devsel# 85 b_pirqd# 2 b_ad[36] 23 b_ad[55] 44 b_ad[8] 65 b_irdy# 86 b_pirqa# 3 b_ad[33] 24 b_ad[53] 45 b_cbe_l[0] 66 b_cbe_l[2] 87 b_ad[28] 4 b_ad[34] 25 b_ad[56] 46 b_ad[7] 67 b_ad[16] 88 b_pirqc# 5 b_ad[39] 26 b_ad[57] 47 b_ad[6] 68 b_frame# 89 b_gnt[0]# 6 b_ad[35] 27 b_ad[58] 48 b_ad[5] 69 b_ad[17] 90 b_pirqb# 7 b_ad[37] 28 b_ad[60] 49 b_ad[4] 70 b_ad[21] 91 b_pclk[1] 8 b_ad[40] 29 b_ad[59] 50 b_ad[9] 71 b_ad[18] 92 b_pclk[0] 9 b_ad[41] 30 b_ad[61] 51 b_m66en 72 b_ad[22] 93 b_gnt[1]# 10 b_ad[38] 31 b_ad[62] 52 b_ad[10] 73 b_ad[19] 94 b_pllclki 11 b_ad[45] 32 b_ad[63] 53 b_ad[11] 74 b_ad[23] 95 b_gnt[2]# 12 b_ad[42] 33 b_par64 54 b_ad[12] 75 b_ad[20] 96 b_pclk[2] 13 b_ad[46] 34 b_cbe_l[4] 55 b_ad[13] 76 b_cbe_l[3] 97 hpsic 14 b_ad[43] 35 b_cbe_l[5] 56 b_ad[14] 77 b_ad[26] 98 b_pllclko 15 b_ad[44] 36 b_cbe_l[6] 57 b_ad[15] 78 b_ad[27] 99 b_req[4]# 16 b_ad[47] 37 b_cbe_l[7] 58 b_cbe_l[1] 79 b_ad[29] 100 b_gnt[3]# 17 b_ad[48] 38 b_req64# 59 b_par 80 b_ad[24] 101 b_pclk[4] 18 b_ad[49] 39 b_ack64# 60 b_serr# 81 b_ad[30] 102 b_gnt[4]# 19 b_ad[50] 40 b_ad[0] 61 b_perr# 82 b_preset# 103 b_pclk[3] 20 b_ad[51] 41 b_ad[1] 62 b_stop# 83 b_ad[25] 104 hpsoc 21 b_ad[52] 42 b_ad[2] 63 b_trdy# 84 b_ad[31]
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 86 nand tree 4: output signal is a_req[3]#. nand tree 5: output signal is b_req[0]#. notes: ? [b, a]_pcixcap, a_req[2:0]#, test, ldtcomp[1:0], p_cal, p_cal#, [b, a]_pme# are not included in the nand trees. ? while in nand-tree mode, the link and pci-x compensation is placed at a mid-band value. ? internal plls are disabled by placing them in bypass mode 10 appendix 10.1 revision history revision 3.01 ? initial release. revision 3.02 ? removed preliminary 1 a_ad[32] 22 a_ad[53] 43 a_ad[5] 64 a_trdy# 85 a_gnt[0]# 2 a_ad[33] 23 a_ad[54] 44 a_ad[6] 65 a_frame# 86 a_preset# 3 a_ad[34] 24 a_ad[55] 45 a_ad[2] 66 a_irdy# 87 a_pclk[0] 4 a_ad[35] 25 a_ad[56] 46 a_ad[1] 67 a_cbe_l[2] 88 a_pirqd# 5 a_ad[36] 26 a_ad[62] 47 a_cbe_l[0] 68 a_ad[18] 89 a_pirqc# 6 a_ad[37] 27 a_ad[61] 48 a_ad[8] 69 a_cbe_l[3] 90 a_pirqb# 7 a_ad[38] 28 a_ad[60] 49 a_ad[9] 70 a_ad[27] 91 a_gnt[1]# 8 a_ad[39] 29 a_ad[59] 50 a_m66en 71 a_ad[16] 92 a_pirqa# 9 a_ad[40] 30 a_ad[58] 51 a_ad[7] 72 a_ad[19] 93 a_pclk[1] 10 a_ad[41] 31 a_ad[57] 52 a_ad[11] 73 a_ad[24] 94 a_gnt[2]# 11 a_ad[42] 32 a_cbe_l[4] 53 a_ad[12] 74 a_ad[29] 95 a_pclk[2] 12 a_ad[43] 33 a_cbe_l[5] 54 a_ad[13] 75 a_ad[20] 96 a_pclk[3] 13 a_ad[44] 34 a_cbe_l[6] 55 a_ad[10] 76 a_ad[25] 97 a_gnt[3]# 14 a_ad[45] 35 a_cbe_l[7] 56 a_ad[14] 77 a_ad[28] 98 a_gnt[4]# 15 a_ad[46] 36 a_par64 57 a_ad[15] 78 a_ad[21] 99 a_pclk[4] 16 a_ad[47] 37 a_ad[63] 58 a_cbe_l[1] 79 a_ad[26] 100 a_pllclki 17 a_ad[48] 38 a_ad[0] 59 a_par 80 a_ad[22] 101 a_req[4]# 18 a_ad[49] 39 a_ack64# 60 a_serr# 81 a_ad[30] 102 a_pllclko 19 a_ad[50] 40 a_req64# 61 a_stop# 82 a_ad[31] 103 a_compat 20 a_ad[51] 41 a_ad[4] 62 a_perr# 83 a_ad[17] 21 a_ad[52] 42 a_ad[3] 63 a_devsel# 84 a_ad[23] 1 hpsod 6 nioairqb# 11 reset# 2 hpsil# 7 refclk 12 strapl[2] 3 strapl[3] 8 nioairqa# 13 cmpovr 4 nioairqc# 9 pwrok 5 nioairqd# 10 ldtstop#
24637 rev 3.02 - august 10, 2004 amd-8131 tm pci-x ? tunnel data sheet 87 ? added error conditions and handling.

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